LFE2-6E-7FN256C Lattice, LFE2-6E-7FN256C Datasheet - Page 21
LFE2-6E-7FN256C
Manufacturer Part Number
LFE2-6E-7FN256C
Description
FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-6E-7FN256C
Number Of Macrocells
6000
Number Of Programmable I/os
190
Data Ram Size
56320
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
LFE2-6E-7FN256C
Manufacturer:
LATTICE
Quantity:
279
Company:
Part Number:
LFE2-6E-7FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE2-6E-7FN256C-6I
Manufacturer:
ZARLINK
Quantity:
7 000
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Lattice Semiconductor
Figure 2-18. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides
of the device. Figure 2-19 shows the selection muxes for these clocks.
Figure 2-19. Edge Clock Mux Connections
Secondary Clock
GPLL Output CLKOP
GPLL Output CLKOS
DLL Output CLKOP
DLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Routing
Vcc
Input Pad
Input Pad
Routing
Routing
Routing
CLKO
CLKO
12
3
1
2-18
16:1
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
Edge Clocks
Edge Clocks
Edge Clocks
(Both Mux)
LatticeECP2/M Family Data Sheet
ECLK1
ECLK2
Slice Control
Architecture
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