LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet
LFE2-6E-7T144C
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... LatticeECP2 Family Data Sheet Version 01.0, February 2006 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2 device. The ispLEVER tool extracts the timing from the rout- ing and back-annotates it into the design for timing verification. ...
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... The LatticeECP2 devices use 1.2V as their core voltage. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Clock Alignment PFU Blocks The core of the LatticeECP2 device consists of PFU blocks which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... FCI To Different Slice/PFU CO F/SUM LUT4 & CARRY LUT4 & CARRY* F/SUM CI FCI From Different Slice/PFU 2-3 Architecture LatticeECP2 Family Data Sheet PFF Block Resources Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM 2 LUT4s Logic, ROM SLICE OFX1 FF* ...
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... Intermediate signal to generate LUT6 and LUT7 F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 Architecture LatticeECP2 Family Data Sheet Description 2 MUX depending on the slice 1 ...
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... PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information on using RAM in LatticeECP2 devices, please see details of additional technical documentation at the end of this data sheet. ...
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... In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not relock until the t parameter has been satisfied. LatticeECP2 devices have two dedicated pins on the left and right LOCK edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at a lower frequency ...
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... The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. For more information on the DLL, please see details of additional technical documentation at the end of this data sheet. ...
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... SMIRDATA O SMI Read Data Delay Chain Delay0 Delay1 Delay2 Reference Delay3 Phase Arithmetic Frequency Delay4 Logic Unit Detector Feedback Description 2-8 Architecture LatticeECP2 Family Data Sheet Duty Cycle 50% Output Muxes Duty Cycle 50% ÷4 ÷2 Lock Detect Digital 9 Control Output CLKOP CLKOS LOCK ...
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... PLL to PLL supported • PLL to DLL supported The DLLs in the LatticeECP2 are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefi ...
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... LatticeECP2 devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeECP2 devices have two to six sysCLOCK PLLs and two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side of the device ...
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... Note: This diagram shows sources for the ECP2-50 device. Smaller devices have fewer SPLLs. Clock Input Clock Input From Routing Primary Clock Sources to Eight Quadrant Clock Selection From Routing Clock Input Clock Input 2-11 Architecture LatticeECP2 Family Data Sheet PLL Input SPLL CLK DIV Clock Input Clock Input DLL Input DLL ...
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... Lattice Semiconductor Secondary Clock/Control Sources LatticeECP2 devices derive secondary clocks (SC0 through EC7) from eight dedicated clock input pads and the rest from routing. Figure 2-9 shows the secondary clock sources. Figure 2-9. Secondary Clock Sources Routing From Routing From Routing Clock Input ...
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... Sources for left edge clocks Primary Clock Routing The clock routing structure in LatticeECP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-11 shows the clock routing for one quadrant. ...
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... DSP block in the DSP row or the center of the DSP row. Figure 2-13 shows this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have eight second- ary clock resources per region (SC0 to SC7). ...
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... Region 8 I/O Bank 4 Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 SC2 SC3 SC4 SC5 8 Secondary Clocks (SC0 to SC7) per Quadrant Control 2-15 Architecture LatticeECP2 Family Data Sheet Vertical Routing Channel Regional Boundary DSP Row Regional Boundary DSP Row Regional Boundary EBR Row Regional Boundary 24:1 24:1 SC6 ...
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... Secondary Clock Edge Clock Routing LatticeECP2 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ- ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the CLKINDEL signal (generated from the DLL_DEL block) is routed to all the edge clock muxes on the left and right sides of the device ...
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... Lattice Semiconductor Figure 2-17. Edge Clock Mux Connections sysMEM Memory LatticeECP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6 ...
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... ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... Block The LatticeECP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Sig- nal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders ...
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... General purpose DSP sysDSP Block Capabilities The sysDSP block in the LatticeECP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP2 family sysDSP Blocks can be either signed or unsigned but not mixed within a function element ...
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... Shift Register B In Multiplicand Multiplier n Input Data Register B Signed Shift Register B Out Shift Register Multiplier Input Data m Register Input To Register Multiplier Shift Register A Out 2-21 Architecture LatticeECP2 Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeECP2 family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. ...
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... Register m m Multiplier Input Data m Register Pipeline m Register Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-23 Architecture LatticeECP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
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... Register m m+n (default) m Multiplier Input Data m Register Pipeline m Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-24 Architecture LatticeECP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-25 Architecture LatticeECP2 Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
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... Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the ispLEVER IPexpress tool which provides the option to configure each DSP module (or group of modules direct HDL instantiation. In addition, Lattice has partnered with The ® MathWorks to support instantiation in the Simulink ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs ...
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... Tristate Register Block Shared Resources IOLD0 Output Register Block DI Input Register Block Control Muxes CLK1 CEO LSR GSR CLK0 CEI PIOB 2-27 Architecture LatticeECP2 Family Data Sheet MMAC TBA TBA TBA TBA TBA TBA PADA “T” sysIO Buffer PADB “C” ...
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... In DDR Mode, two registers are used to sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1. LatticeECP2 Family Data Sheet Description Clock enables for input and output block flip-flops ...
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... Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-29 Architecture LatticeECP2 Family Data Sheet INCK** To DQS Delay Block** INDD Clock Transfer Registers IPOS0A QPOS0A D-Type /LATCH D-Type* IPOS1A QPOS1A D-Type D-Type* /LATCH ...
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... ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2- 29 shows the diagram using this gearbox function. For more information on this topic, please see information regarding additional documentation at the end of this data sheet. LatticeECP2 Family Data Sheet Q D ...
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... Shared with output register Latch Latch Note: Simplified version does not show CE and SET/RESET details 2-31 Architecture LatticeECP2 Family Data Sheet D-Type 1 /LATCH D-Type Latch DDR Output D Q Registers D-Type /LATCH 0 1 ...
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... PICs on these edges have registered elements that support DDR memory interfaces. One of every 18 PIOs con- tains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the set of 18 PIOs. Figure 2-31 shows the assignment of DQS pins in each set of 18 PIOs. LatticeECP2 Family Data Sheet Q D ...
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... Figure 2-30. DQS Routing for the Left and Right Edges of the Device DQS LatticeECP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" ...
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... DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-32. The DLL loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. LatticeECP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB " ...
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... Figure 2-32. DLL Calibration Bus and DQS/DQS Transition Distribution Spans 16 PIOs I DQS Input 7 I Spans 18 PIOs I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 4 I/O Bank 5 2-35 Architecture LatticeECP2 Family Data Sheet ECLK1 ECLK2 I Delayed DQS DQS Transition I/O distribution DQSXFER DQS Delay k Control Bus 3 ...
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... In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
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... Lattice Semiconductor DQSXFER LatticeECP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysIO Buffer Each I/O is associated with a flexible buffer referred sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’ ...
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... V REF1(6) V REF2(6) GND LatticeECP2 devices contain two types of sysIO buffer pairs. 1. Top (Bank 0 and Bank 1) sysIO Buffer Pairs (Single-Ended Outputs Only) The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- fi ...
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... CCIO all the I/O banks that are critical to the application. For more information on controlling the output logic state with valid input logic levels during power-up in LatticeECP2 devices, see details of additional technical documentation at the end of this data sheet. The V ...
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... Differential SSTL2 Class I, II Differential SSTL3 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS 1 When not specified, V can be set anywhere in the valid operating range. CCIO LatticeECP2 Family Data Sheet V (Nom.) V REF — — — ...
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... In addition, leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeECP2 ideal for many multiple power supply and hot-swap applications. LatticeECP2 Family Data Sheet ...
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... TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur- ing device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. See Lattice technical note number TN1087, Minimizing System Interruption During Confi ...
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... LatticeECP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during down or incorrect version number with this new boot image, the LatticeECP2 device can revert back to the orig- inal backup configuration and try again. This all can be done without power cycling the system. ...
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... Lattice Semiconductor Density Shifting The LatticeECP2 family is designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower utilization design tar- geted for a high-density device to a lower density device. However, the exact details of the fi ...
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... Note this table represents DC conditions. For the first 20ns after hot insertion, current specification is 8mA. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO 1.2V (MAX 3-2 DC and Switching Characteristics LatticeECP2 Family Data Sheet Min. Typ. Max. — — 10 -30 — -210 30 — 210 30 — — -30 — — — — 210 — — -210 ...
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... Pattern represents a “blank” configuration data file power supplies at nominal voltage Per bank Over Recommended Operating Conditions Parameter 6 3-3 DC and Switching Characteristics LatticeECP2 Family Data Sheet 5 Device Typical ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ...
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... Per bank Over Recommended Operating Conditions Parameter ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 7 3-4 DC and Switching Characteristics LatticeECP2 Family Data Sheet 5 Device Typical or GND. CCIO Units ...
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... CCIO 3-5 LatticeECP2 Family Data Sheet V (V) REF Typ. Max. — — — — — — — — — — — — — — — — — — — — — 0.9 0.969 1 ...
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... REF - 0 0.2 3.6 REF - 0. 0.18 3.6 REF - 0. 0.18 3.6 REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-6 DC and Switching Characteristics LatticeECP2 Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 16, 12, ...
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... LVDS25E The top and bottom sides of LatticeECP2 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. ...
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... Output High Voltage (after Output Low Voltage (after Output Differential Voltage (After Output Common Mode Voltage CM Z Back Impedance BACK I DC Output Current DC DC and Switching Characteristics LatticeECP2 Family Data Sheet Description Typical 2.50 20 158 140 100 ) 1. 1. 0.35 1 1.25 100.5 6 ...
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... Lattice Semiconductor BLVDS The LatticeECP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeECP2 devices support the differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
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... Lattice Semiconductor RSDS The LatticeECP2 devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LatticeECP2 devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... Through or Normal, PLC Output Regis- ters) Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x2 Pseudo-Dual Port RAM 64x1 Pseudo-Dual Port RAM DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) DC and Switching Characteristics LatticeECP2 Family Data Sheet 1 -7 Timing 6.4 10.0 18.4 3.6 3.6 4.1 4.6 ...
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... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics LatticeECP2 Family Data Sheet -7 Timing 422 TBA ...
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... LFEC2-50 — LFEC2-50 — LFEC2-50 — LFEC2-50 LFEC2-50 — LFEC2-50 — LFEC2-50 — LFEC2-50 LFEC2-50 — LFEC2-50 — LFEC2-50 LFEC2-50 3-15 DC and Switching Characteristics LatticeECP2 Family Data Sheet -6 -5 Max. Min. Max. Min. Max. 3.49 — 3.79 — — 0.15 — 0.09 — 0.11 — 0.23 — — ...
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... Lattice Semiconductor LatticeECP2 External Switching Characteristics (Continued) Parameter Description t Data Invalid Before Strobe/Clock DQVBCLKXGMII t Data Invalid After Strobe/Clock DQVACLKXGMII Primary f Frequency for Primary Clock Tree MAX_PRI t Clock Pulse Width for Primary Clock LFEC2-50 W_PRI t Primary Clock Skew Within a Device LFEC2-50 SKEW_PRI ...
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... Figure 3-8. XGMII Receiver Parameters RXCLK RXC, RXD Tsu Figure 3-9. DDR1, DDR2, SPI4.2, SFI4 Receiver Parameters CLOCK OR STROBE (e.g. RDCLK in SPI-4.2) DATA (e.g. RDAT[15:0], RCTL in SPI-4.2) Tdvaclk (or dq) Tdveclk (or dq) DC and Switching Characteristics * known as Tsu driver in XGMII * known as Th driver in XGMII Th Tsu Th 3-17 LatticeECP2 Family Data Sheet ...
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... HWREN_EBR (Write/Read Clk) Over Recommended Operating Conditions -7 Min. — — — — — — — — — — 3-18 DC and Switching Characteristics LatticeECP2 Family Data Sheet Max. Min. Max. Min. Max. — — — — — — — — — — ...
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... Internal parameters are characterized but not tested on every device. 2. These parameters include the Adder Subtractor block in the path. Timing v. Over Recommended Operating Conditions -7 Min. — — — — — — 3-19 DC and Switching Characteristics LatticeECP2 Family Data Sheet 1 (Continued Max. Min. Max. Min. Max. — — — — ...
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... Mem(n) data from previous read DOA (Regs DOA Mem(n) data from previous read output is only updated during a read cycle 3-20 DC and Switching Characteristics LatticeECP2 Family Data Sheet ACCESS ACCESS ACCESS ACCESS ...
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... Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock ACCESS ACCESS ACCESS old A0 Data old A1 Data Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-21 DC and Switching Characteristics LatticeECP2 Family Data Sheet ACCESS ACCESS ACCESS ...
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... BLVDS25 BLVDS 2.5 4 LVPECL33 LVPECL 3.3 HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 3-22 DC and Switching Characteristics LatticeECP2 Family Data Sheet - Units ...
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... LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-23 DC and Switching Characteristics LatticeECP2 Family Data Sheet - Units ...
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... LVCMOS timing measured with the load specified in Switching Test Conditions table. 3. All other standards according to the appropriate specification. 4. These timing adders are measured with the recommended resistor values. Timing (Continued) Over Recommended Operating Conditions Description 3-24 DC and Switching Characteristics LatticeECP2 Family Data Sheet - Units ...
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... OUT f < 100 MHz OUT N/M = integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without capacitor With capacitor 3-25 DC and Switching Characteristics LatticeECP2 Family Data Sheet Min. Typ. Max. — 420 — — 420 — — 840 — — ...
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... MHz OUT N/M = Integer At 90% or 10% Without external capacitor With external capacitor 90% to 90% 10% to 10% Without external capacitor With external capacitor 3-26 DC and Switching Characteristics LatticeECP2 Family Data Sheet Min. Typ. Max. — 420 — — 420 — — 840 — ...
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... CLKOP runs at the same frequency as the input clock. 2. CLKOS minimum frequency is obtained with divide This is intended “path-matching” design guideline and is not a measurable specification. Over Recommended Operating Conditions Description 3-27 DC and Switching Characteristics LatticeECP2 Family Data Sheet Min. Typ. Max. — 420 — ...
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... Lattice Semiconductor LatticeECP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t CCLK to DOUT in Flowthrough Mode CODO t CSN[0:1] Setup Time to CCLK SUCS t CSN[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
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... Lattice Semiconductor LatticeECP2 sysCONFIG Port Timing Specifications (Continued) Parameter Max. CCLK Frequency - SPI Flash Read Opcode (0x03) (SPIFASTN = 1) f MAXSPI Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B) (SPIFASTN = 0) t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK ...
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... BSCAN test update register, falling edge of clock to valid disable BTUODIS t BSCAN test update register, falling edge of clock to valid enable BTUPOEN Timing v. Over Recommended Operating Conditions Parameter 3-30 DC and Switching Characteristics LatticeECP2 Family Data Sheet Min Max — — — — — — — ...
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... Includes Test Fixture and Probe Capacitance ∞ ∞ ∞ 1MΩ ∞ 1MΩ ∞ 100 ∞ 100 3-31 DC and Switching Characteristics LatticeECP2 Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
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... Test and Programming (Dedicated Pins) TMS © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Output for serial configuration data (rising edge of CCLK) when using O sysCONFIG port. Input for serial configuration data (clocked with CCLK) when using sysCON- I/O FIG port. During configuration, a pull-up is enabled. Output when used in SPI/ SPIX modes. 4-2 Pinout Information LatticeECP2 Family Data Sheet Description ...
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... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LatticeECP2 Family Data Sheet DDR Strobe (DQS) and PIO Within PIC ...
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... Dedicated Muxed Bank0 Bank1 Bank2 Bank3 Bank4 Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 Bank4 Bank5 Bank6 Bank7 4-4 Pinout Information LatticeECP2 Family Data Sheet Package 672 fpBGA — — — — — — — ...
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... L17, L24, L3, M13, M14, N10, N12, N13, N14, N15, N17, P10, P12, P13, P14, P15, P17, R13, R14, T10, T11, T16, T17, T24, T3, U10, U11, U13, U14, U16, U17, V13, V14, V21, V6 N6, P24, M3 4-5 Pinout Information LatticeECP2 Family Data Sheet 672 fpBGA ...
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... H3 PL14A VCCIO VCCIO H4 PL14B J5 PL15A VCC VCC J4 PL15B J3 PL16A GND GNDIO GND GND K4 PL16B H1 PL17A H2 PL17B VCCIO VCCIO K6 PL18A K7 PL18B LatticeECP2 Family Data Sheet Bank Dual Function 7 VREF2_7 7 VREF1_7 LDQS8 ...
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... VCC VCC 4-7 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential C C LDQS24 T* C* LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A C LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A LDQS41 ...
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... PL55A U2 PL55B VCCIO VCCIO V2 PL56A W2 PL56B VCC VCC T6 PL57A R5 PL57B GND GNDIO GND GND R6 PL58A R7 PL58B W1 PL59A VCCIO VCCIO Y2 PL59B LatticeECP2 Family Data Sheet Bank Dual Function 7 PCLKT7_0 7 7 PCLKC7_0 7 6 PCLKT6_0 6 6 PCLKC6_0 6 VREF2_6 6 VREF1_6 LDQS50 ...
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... PL71A W5 PL71B AC1 PL72A AD1 PL72B VCCIO VCCIO Y6 PL73A Y5 PL73B VCC VCC AE2 PL74A AD2 PL74B GND GNDIO GND GND AB3 PL75A LatticeECP2 Family Data Sheet Bank Dual Function 6 LLM0_GDLLT_IN_A 6 LLM0_GDLLC_IN_A 6 LLM0_GDLLT_FB_A 6 6 LLM0_GDLLC_FB_D LLM0_GPLLT_IN_A 6 6 LLM0_GPLLC_IN_A 6 LLM0_GPLLT_FB_A 6 LLM0_GPLLC_FB_A 6 ...
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... AB7 PB8B VCCIO VCCIO AE5 PB9A AF5 PB9B AC7 PB10A AD7 PB10B GND GNDIO GND GNDAUX GND GND VCCIO VCCIO VCC VCC GND GNDIO LatticeECP2 Family Data Sheet Bank Dual Function VREF2_5 5 VREF1_5 5 5 ...
Page 89
... VCC VCC 4-11 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential BDQS24 BDQS33 ...
Page 90
... VCC VCC 4-12 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential BDQS42 PCLKT5_0 T PCLKC5_0 C PCLKT4_0 T PCLKC4_0 BDQS51 T ...
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... AA19 PB65A GND GND W17 PB65B Y19 PB66A Y17 PB66B AF20 PB67A VCCIO VCCIO AE20 PB67B AA20 PB68A VCC VCC W18 PB68B AD20 PB69A LatticeECP2 Family Data Sheet Bank Dual Function BDQS60 4 ...
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... VCC 4-14 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential BDQS78 VREF2_4 T VREF1_4 C WRITEN C CS1N T CSN C ...
Page 93
... U26 PR65A VCCIO VCCIO U22 PR64B U23 PR64A U24 PR63B U25 PR63A VCCAUX VCCAUX R20 RLM0_PLLCAP P18 RLM0_VCCPLL GND GNDAUX T19 PR61B U20 PR61A LatticeECP2 Family Data Sheet Bank Dual Function ...
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... N19 PR49B N20 PR49A VCC VCC M26 PR48B M25 PR48A VCCIO VCCIO N18 PR47B N21 PR47A L26 PR46B L25 PR46A VCCAUX VCCAUX GND GNDAUX LatticeECP2 Family Data Sheet Bank Dual Function 3 3 RLM0_GDLLC_IN_A 3 RLM0_GDLLT_IN_A RDQS58 ...
Page 95
... VCC VCC 2 4-17 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential PCLKC2_0 PCLKT2_0 RDQS41 RUM0_SPLLC_FB_A RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A C* RDQS24 ...
Page 96
... H21 PR8B G22 PR8A GND GND B24 PR7B GND GNDIO C24 PR7A D23 PR6B VCC VCC C23 PR6A G21 PR5B VCCIO VCCIO H20 PR5A LatticeECP2 Family Data Sheet Bank Dual Function RDQS16 ...
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... VCCIO B21 PT70B B20 PT70A D19 PT69B B19 PT69A GND GNDIO G17 PT68B E18 PT68A VCC VCC G19 PT67B F17 PT67A VCCIO VCCIO LatticeECP2 Family Data Sheet Bank Dual Function 2 2 VREF2_2 2 VREF1_2 1 1 VREF2_1 1 1 VREF1_1 ...
Page 98
... B14 PT55A GND GNDIO C15 PT54B A15 PT54A A13 PT53B B13 PT53A VCCIO VCCIO H17 PT52B H15 PT52A D13 PT51B C14 PT51A GND GNDIO LatticeECP2 Family Data Sheet Bank Dual Function ...
Page 99
... VCC 4-21 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential PCLKC1_0 C PCLKT1_0 T PCLKC0_0 C PCLKT0_0 ...
Page 100
... VCC VCC 4-22 Pinout Information LatticeECP2 Family Data Sheet Dual Function Differential ...
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... PT6B VCC VCC C1 PT6A G8 PT5B GND GNDIO G7 PT5A E7 PT4B VCCIO VCCIO F7 PT4A E6 PT3B E5 PT3A G6 PT2B VCCAUX VCCAUX G5 PT2A *Supports dedicated LVDS outputs. LatticeECP2 Family Data Sheet Bank Dual Function VREF2_0 0 0 ...
Page 102
... Note: LatticeECP2 devices are dual marked. For example, the commercial speed grade LFE2-50E-7F672C is also marked with industrial grade -6I (LFE2-50E-6F672I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings. ...
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... Lattice Semiconductor Part Number I/Os LFE2-50E-5F484I 339 LFE2-50E-6F484I 339 LFE2-50E-5F672I 500 LFE2-50E-6F672I 500 Industrial Voltage Grade Package 1.2V -5 fpBGA 1.2V -6 fpBGA 1.2V -5 fpBGA 1.2V -6 fpBGA 5-2 Ordering Information LatticeECP2 Family Data Sheet Pins Temp. LUTs (K) 484 IND 484 IND 672 IND 672 IND ...
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