LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 2

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

February 2006
Features
■ High Logic Density for System Integration
■ sysDSP™ Block
■ Flexible Memory Resources
■ sysCLOCK Analog PLLs And DLLs
■ Pre-Engineered Source Synchronous I/O
Table 1. LatticeECP2 Family Selection Guide
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LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
GPLL + SPLL + GDLL
Maximum Available I/O
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
• 6K to 68K LUTs
• 192 to 628 I/Os
• 3 to 22 blocks for high performance multiply and
• 12 to 88 18x18 multipliers
• Each block supports
• 55Kbits to 1032Kbits sysMEM™ Embedded
• 12K to 136Kbits distributed RAM
• Two GPLLs and up to four SPLLs per device
• Two general purpose DLLs per device
• Dedicated DQS support
• DDR registers in I/O cells
• Dedicated gearing logic
accumulate
Block RAM (EBR) 18-Kbit block
– One 36x36 multiplier or four 18X18 or eight
– Single, pseudo dual and true dual port
– Single port and pseudo dual port
– Clock multiply, divide, phase adjust and
Device
9X9 multipliers
delay adjust
ECP2-6
2+0+2
192
192
12
55
12
95
6
3
3
ECP2-12
2+0+2
LatticeECP2 Family Data Sheet
221
297
127
192
297
12
24
12
24
95
6
1-1
■ Programmable sysIO™ Buffer Supports
■ Flexible Device Configuration
■ Optional Bitstream Encryption
■ System Level Support
ECP2-20
2+0+2
Wide Range Of Interfaces
276
363
127
192
332
363
21
42
15
28
• Source synchronous standards support
• Dedicated DDR and DDR2 memory support
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
• 1149.1 Boundary Scan compliant
• Dedicated bank for configuration for I/Os
• SPI boot flash interface
• Dual boot images supported
• Encrypted bit stream support
• TransFR™ I/O for simple field updates
• Optional Soft Error Detect macro embedded
• ispTRACY™ internal logic analyzer capability
• Onboard oscillator for initialization and general
• 1.2V power supply
7
use
– SPI4.2, SFI4, XGMII
– High Speed ADC/DAC devices
– DDR1 400 (200MHz)
– DDR2 400 (200MHz)
ECP2-35
2+0+2
332
452
332
452
32
64
18
32
8
Introduction
ECP2-50
2+2+2
387
500
339
500
48
21
18
72
96
Advance Data Sheet
Introduction_01.0
ECP2-70
2+4+2
1032
136
628
500
628
68
56
22
88