LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 17

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-11. Per Quadrant Primary Clock Selection
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is
toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block
come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-
11).
Figure 2-12 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information on the DCS, please see details of additional technical documentation at the
end of this data sheet.
Figure 2-12. DCS Waveforms
Secondary Clock/Control Routing
Secondary clocks in the LatticeECP2 devices are region-based resources. EBR/DSP rows and a special vertical
routing channel bound the secondary clock regions. This special vertical routing channel aligns with either the left
edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-13 shows this special vertical
routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have eight second-
ary clock resources per region (SC0 to SC7).
The secondary clock muxes are located in the center of the device. Figure 2-13 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for high fan-out control and SC4 to SC7 are used
for clock signals.
CLK0
35:1
SEL
CLK1
CLK0
DCSOUT
CLK1
35:1
Primary Clock Feedlines: PLLs + DLLs + CLKDIVs + PIOs + Routing
CLK2
35:1
8 Primary Clocks (CLK0 to CLK7) per Quadrant
CLK3
35:1
CLK4
35:1
2-14
CLK5
35:1
32:1
CLK6
DCS
LatticeECP2 Family Data Sheet
32:1
32:1
CLK7
DCS
32:1
Architecture