LFE2-6E-7T144C Lattice, LFE2-6E-7T144C Datasheet - Page 33

• Manufacturer Part Number: LFE2-6E-7T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-27. Input Register Block Top Edge
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contains a register for SDR operation that
is combined with an additional latch for DDR operation. Figure 2-28 shows the diagram of the Output Register
Block for PIOs on the left, right and the bottom edges. Figure 2-29 shows the diagram of the Output Register Block
for PIOs on the top edge of the device.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers is fed into registers on the positive edge of
the clock. Then at the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock
selects the correct register for feeding to the output (D0).
By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox
function can be implemented, that takes four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-
29 shows the diagram using this gearbox function. For more information on this topic, please see information
regarding additional documentation at the end of this data sheet.
(from sysIO
routing)
buffer)
CLK0
(from
DI
Note: Simplified version does not show CE and SET/RESET details.
*On selected blocks.
Fixed Delay
2-30
D
/LATCH
D-Type
Q
LatticeECP2 Family Data Sheet
INCK*
* I NDD
IPOS0
Architecture