AGLP060V2-CSG289 Actel, AGLP060V2-CSG289 Datasheet - Page 23
AGLP060V2-CSG289
Manufacturer Part Number
AGLP060V2-CSG289
Description
FPGA - Field Programmable Gate Array 60K System Gates
Manufacturer
Actel
Datasheet
1.AGLP125V5-CSG289.pdf
(128 pages)
Specifications of AGLP060V2-CSG289
Processor Series
AGLP060
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
4
Data Ram Size
4608 bit
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
60 K
Package / Case
CSP-289
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3 V LVCMOS Wide Range
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
2.5 V LVCMOS – Schmitt Trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt Trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.2 V LVCMOS
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
1.2 V LVCMOS Wide Range
Notes:
1. PAC9 is the total dynamic power measured on VCCI.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI ≥ VCC.
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PAC10 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO PLUS V2 devices only, operating at VCCI ≥ VCC.
Power per I/O Pin
3
3
4
– Schmitt Trigger
2
2
3
3
3
4
– Schmitt Trigger
– Schmitt Trigger
C
LOAD
5
5
5
5
5
5
5
R ev i si o n 1 1
(pF)
VCCI (V)
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
1.2
1.2
VCCI (V)
3.3
3.3
2.5
1.8
1.5
1.2
1.2
IGLOO PLUS Low Power Flash FPGAs
PAC9 (µW/MHz)
Dynamic Power
PAC10 (µW/MHz)
1
Dynamic Power
16.26
18.95
16.26
18.95
4.59
6.01
1.61
1.70
0.96
0.90
0.55
0.47
0.55
0.47
127.11
127.11
70.71
35.57
24.30
15.22
15.22
1
2
2 -9
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