A3P400-PQG208 Actel, A3P400-PQG208 Datasheet - Page 106
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A3P400-PQG208
Manufacturer Part Number
A3P400-PQG208
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-PQG208
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3 DC and Switching Characteristics
Clock Conditioning Circuits
Table 2-115 • ProASIC3 CCC/PLL Specification
2- 92
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Serial Clock (SCLK) for Dynamic PLL
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
2. This delay is a function of voltage and temperature. See
3. T
4. The A3P030 device does not contain a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
temperature and voltage supply levels, refer to
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
(A3P250 and A3P1000 only)
(all other dies)
(A3P250 and A3P1000 only)
(all other dies)
J
= 25°C, VCC = 1.5 V
CCC Electrical Specifications
Timing Characteristics
5
2, 3
1
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
CCC_OUT
IN_CCC
2, 3
2, 3
OUT_CCC
Table 2-6 on page 2-6
2, 3
Table 2-6 on page 2-6
R e visio n 9
Minimum
1 Global
Network
0.50%
1.00%
1.75%
2.50%
0.225
Used
0.75
48.5
1.5
0.6
for derating values.
Max Peak-to-Peak Period Jitter
Typical
for deratings.
200
2.2
Maximum
Networks
3 Global
0.70%
1.20%
2.00%
5.60%
Used
51.5
5.56
5.56
350
300
300
300
350
125
1.5
6.0
1.6
1.6
1.6
0.8
32
Units
MHz
MHz
MHz
ms
µs
µs
ps
ns
µs
ns
ns
ns
ns
ns
ns
ns
%
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