A3P400-PQG208 Actel, A3P400-PQG208 Datasheet - Page 27
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A3P400-PQG208
Manufacturer Part Number
A3P400-PQG208
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-PQG208
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
N
α
F
P
N
N
α
F
P
N
α
F
P
N
α
β
F
P
N
F
β
F
β
P
F
CLK
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
C-CELL
NET
INPUTS
OUTPUTS
MEMORY
PLL
C-CELL
S-CELL
C-CELL
INPUTS
OUTPUTS
1
BLOCKS
2
3
1
1
2
2
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the RAM enable rate for write operations—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
= P
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
= (N
= N
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
= N
DC4
is the number of I/O input buffers used in the design.
is the output clock frequency.
is the number of RAM blocks used in the design.
S-CELL
= P
= N
is the number of I/O output buffers used in the design.
C-CELL
INPUTS
+ P
AC11
is the memory read clock frequency.
OUTPUTS
is the memory write clock frequency.
AC13
+ N
*
* N
*
α
C-CELL
α
PLL
*F
BLOCKS
1
MEMORY
2
/ 2 * P
*
CLKOUT
/ 2 * P
α
) *
2
/ 2 *
AC7
* F
α
NET
AC9
1
READ-CLOCK
β
/ 2 * P
* F
INPUTS
* F
1
CLK
* P
OUTPUTS
CLK
1
AC8
AC10
C-CELL
R e v i s i o n 9
* F
* F
*
AC14
CLK
β
CLK
2
+ P
* F
CLKOUT
AC12
* N
Table 2-16 on page
Table 2-16 on page
Table 2-17 on page
product) to the total PLL contribution.
BLOCK
* F
Table 2-16 on page
Table 2-16 on page
WRITE-CLOCK
ProASIC3 Flash Family FPGAs
Table 2-17 on page
2-14.
2-14.
2-14.
*
β
3
2-14.
2-14.
2-14.
2- 13
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