LFXP15C-3FN256C Lattice, LFXP15C-3FN256C Datasheet - Page 37
LFXP15C-3FN256C
Manufacturer Part Number
LFXP15C-3FN256C
Description
FPGA - Field Programmable Gate Array 15.4K LUTS 188 I/O
Manufacturer
Lattice
Specifications of LFXP15C-3FN256C
Number Of Programmable I/os
188
Data Ram Size
331776
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP15C-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Table 2-8. Supported Output Standards
Hot Socketing
The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os
remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits, which allows easy integration with the rest of the system.
These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications.
Sleep Mode
The LatticeXP “C” devices (V
to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the
SLEEPN pin.
During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os
are tri-stated. Do not enter Sleep Mode during device programming or configuration operation. In Sleep Mode,
power supplies can be maintained in their normal operating range, eliminating the need for external switching of
power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes.
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS
LVPECL
1. Emulated with external resistors.
1
1
Output Standard
CC
= 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
2-25
4mA, 8mA, 12mA 16mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA
2mA. 6mA
Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LatticeXP Family Data Sheet
V
CCIO
3.3
3.3
2.5
1.8
1.5
1.2
3.3
1.8
1.5
3.3
2.5
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
—
1.8
—
—
—
—
(Nom.)
Architecture
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