AGLN020V2-QNG68 Actel, AGLN020V2-QNG68 Datasheet - Page 91
AGLN020V2-QNG68
Manufacturer Part Number
AGLN020V2-QNG68
Description
FPGA - Field Programmable Gate Array 20K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN020V2-QNG68
Processor Series
AGLN020
Core
IP Core
Number Of Macrocells
172
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
49
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
20 K
Package / Case
QFN-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN020V2-QNG68
Manufacturer:
ATECH
Quantity:
1 250
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Table 2-103 • RAM4K9
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWL
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
1.5 V DC Core Voltage
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same address; applicable
to closing edge
Address collision clk-to-clk delay for reliable read access after write on same address;
applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same address;
applicable to opening edge
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Description
R ev i si o n 1 1
Table 2-6 on page 2-6
IGLOO nano Low Power Flash FPGAs
for derating values.
0.69
0.13
0.68
0.13
1.37
0.13
0.59
0.30
2.94
2.55
1.51
0.23
0.35
0.41
1.72
1.72
0.51
2.68
0.68
6.24
Std. Units
160
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 77
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