LFE2M20SE-5FN484C Lattice, LFE2M20SE-5FN484C Datasheet - Page 113

• Manufacturer Part Number: LFE2M20SE-5FN484C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN484C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 304
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.)
Available DDR-Interfaces per I/O
Bank
PCI Capable I/Os per Bank
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
1
Pin Type
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
4-10
484 fpBGA
46
46
0
0
2
0
3
3
1
2
0
0
0
0
0
0
0
0
LFE2-50
LatticeECP2/M Family Data Sheet
672 fpBGA
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
672 fpBGA
Pinout Information
62
68
0
0
3
3
4
4
4
3
0
0
0
0
0
0
0
0
LFE2-70
900 fpBGA
72
80
0
0
4
3
4
5
4
4
0
0
0
0
0
0
0
0