A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 83
A3P400-FGG484
Manufacturer Part Number
A3P400-FGG484
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-FGG484
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
R
T
Z
Z
Z
stub
0
0
Receiver
+
R
R
S
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A
sample application is given in
section in
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R
R
-
T
EN
R
Z
= 70 Ω, given Z
S
stub
Z
Z
Table
Z
0
0
stub
Transceiver
+
2-92.
R
T
S
0
-
= 50 Ω (2") and Z
EN
R
Z
stub
S
Z
Z
Z
0
0
Figure
stub
Driver
+
R
D
S
2-12. The input and output buffer delays are available in the LVDS
stub
-
EN
R
Z
S
stub
= 50 Ω (~1.5").
R e v i s i o n 9
Z
Z
Z
0
0
stub
Receiver
+
R
R
S
-
EN
R
Z
S
stub
...
Z
Z
0
0
Transceiver
ProASIC3 Flash Family FPGAs
+
R
T
S
-
EN
R
S
S
BIBUF_LVDS
= 60 Ω and
Z
Z
0
0
2- 69
R
T
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