AGLN010V2-UCG36 Actel, AGLN010V2-UCG36 Datasheet - Page 45

FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano

AGLN010V2-UCG36

Manufacturer Part Number
AGLN010V2-UCG36
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet

Specifications of AGLN010V2-UCG36

Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
23
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
10 K
Package / Case
uCSP-36
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage
Table 2-44 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
3. Software default selection highlighted in gray.
equivalent software default drive strength. These values are for normal ranges only.
equivalent software default drive strength. These values are for normal ranges only.
Equivalent
Software
Default
Drive
Strength
Option
Equivalent
Software
Default
Drive
Strength
Option
Commercial-Case Conditions: T
Commercial-Case Conditions: T
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
Applies to 1.2 V DC Core Voltage
1
1
Speed
Speed
Grade
Grade
STD
STD
STD
STD
STD
STD
STD
STD
t
t
DOUT
1.55
1.55
1.55
1.55
DOUT
1.55
1.55
1.55
1.55
3.82
3.82
3.25
3.25
6.01
6.01
5.02
5.02
t
t
DP
DP
J
J
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V
0.26
0.26
0.26
0.26
0.26
0.26
0.26
0.26
t
t
DIN
DIN
R ev i si o n 1 1
1.31
1.31
1.31
1.31
1.31
1.31
1.31
1.31
t
t
PY
PY
t
1.91
1.91
1.91
1.91
t
1.91
1.91
1.91
1.91
Table 2-6 on page 2-6
PYS
Table 2-6 on page 2-6
PYS
t
t
EOUT
1.10
1.10
1.10
1.10
EOUT
1.10
1.10
1.10
1.10
3.82
3.82
3.25
3.25
IGLOO nano Low Power Flash FPGAs
6.01
6.01
5.02
5.02
t
t
ZL
ZL
for derating values.
for derating values.
3.15
3.15
2.61
2.61
5.66
5.66
4.76
4.76
t
t
ZH
ZH
3.01
3.01
3.38
3.38
3.02
3.02
3.38
3.38
t
t
LZ
LZ
3.65
3.65
4.27
4.27
3.49
3.49
4.10
4.10
t
t
HZ
HZ
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
2- 31

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