AGLN015V2-QNG68 Actel, AGLN015V2-QNG68 Datasheet - Page 58

• Manufacturer Part Number: AGLN015V2-QNG68
• Description: FPGA - Field Programmable Gate Array 15K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN015V2-QNG68

• Processor Series: AGLN015
• Core: IP Core
• Number Of Macrocells: 128
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 49
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 15 K
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano DC and Switching Characteristics
Table 2-71 • Parameter Definition and Measuring Nodes
2- 44
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OCLR2Q
OREMCLR
ORECCLR
OECLKQ
OESUD
OEHD
OECLR2Q
OEREMCLR
OERECCLR
ICLKQ
ISUD
IHD
ICLR2Q
IREMCLR
IRECCLR
See
Figure 2-13 on page 2-43
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 1
Measuring Nodes
(from, to)*
HH, DOUT
HH, EOUT
LL, DOUT
II, EOUT
CC, AA
DD, AA
AA, EE
CC, AA
DD, EE
DD, AA
FF, HH
FF, HH
LL, HH
LL, HH
JJ, HH
JJ, HH
II, HH
II, HH