LFXP10C-3FN256I Lattice, LFXP10C-3FN256I Datasheet - Page 237

• Manufacturer Part Number: LFXP10C-3FN256I
• Description: FPGA - Field Programmable Gate Array 9.7K LUTs 188 IO 1.8 /2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP10C-3FN256I

• Number Of Programmable I/os: 188
• Data Ram Size: 221184
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Some reference documents that discuss board layout guidelines:
References
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
• www.idt.com, IDT, PCB Design for Double Data Rate Memory.
• www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces.
• www.micron.com, TN4607, DDR 333 Design Guide for Two DIMM Systems
• www.jedec.org – JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification
• www.micron.com – DDR SDRAM Data Sheets
• www.infinion.com – DDR SDRAM Data Sheets
• www.samsung.com – DDR SDRAM Data Sheets
• www.latticesemi.com – RD1019 QDR Memory Controller Reference Design for LatticeECP/EC devices
• www.toshiba.com – DDR FCRAM Data Sheet
• www.fujitsu.com – DDR FCRAM Data Sheet
• www.latticesemi.com – LatticeEC Advanced Evaluation Board User’s Guide
• www.latticesemi.com – DDR SDRAM Controller (Pipelined Version for LatticeECP/EC Devices) User's
February 2007
Guide
[phone] (Outside North America)
[e-mail]
Date
—
Version
03.2
—
Previous Lattice releases.
Updated Generic High Speed DDR Implementation section.
Updated Appendix D.
10-18
Change Summary
LatticeECP/EC and LatticeXP
DDR Usage Guide