AGL1000V2-FGG484 Actel, AGL1000V2-FGG484 Datasheet - Page 83
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
AGL1000V2-FGG484
Manufacturer Part Number
AGL1000V2-FGG484
Description
FPGA - Field Programmable Gate Array 1M System Gates IGLOO
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL1000V2-FGG484
Processor Series
AGL1000
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
300
Data Ram Size
147456
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL1000V2-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL1000V2-FGG484I
Manufacturer:
Actel
Quantity:
2
Company:
Part Number:
AGL1000V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL1000V2-FGG484I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
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Table 2-112 • Minimum and Maximum DC Input and Output Levels
Figure 2-10 • AC Loading
Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = Vtrip. See
larger when operating outside recommended ranges
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is
Min.
–0.3 0.35 * VCCI 0.65 * VCCI
V
Applicable to Standard I/O Banks
Test Point
Datapath
VIL
Max.
V
Table 2-28 on page 2-28
5 pF
Min.
Input High (V)
V
VIH
1.5
Enable Path
Max.
Test Point
3.6
V
R = 1 k
0.25 * VCCI 0.75 * VCCI
for a complete table of trip points.
R ev i si o n 1 8
Max.
VOL
V
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
0.75
VOH
Min.
V
HZ
ZH
/ t
HZ
LZ
/ t
mA mA
LZ
I
OL
2
ZHS
/ t
/ t
ZL
ZH
I
OH
2
/ t
IGLOO Low Power Flash FPGAs
/ t
/ t
ZL
ZLS
ZHS
Max.
mA
I
/ t
OSH
13
ZLS
3
C
LOAD
Max.
mA
I
5
OSL
16
(pF)
3
µA
I
IL
10 10
1
4
µA
2- 69
I
IH
2
4
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