A3P125-PQG208 Actel, A3P125-PQG208 Datasheet - Page 69

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A3P125-PQG208

Manufacturer Part Number
A3P125-PQG208
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3P125-PQG208

Processor Series
A3P125
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3P125-PQG208
Manufacturer:
ACT
Quantity:
5
Part Number:
A3P125-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P125-PQG208
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Part Number:
A3P125-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-70 • 1.8 V LVCMOS High Slew
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Applicable to Advanced I/O Banks
Timing Characteristics
Speed
Grade
Std.
Std.
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
10.09
11.86
8.86
6.91
5.88
5.16
4.45
3.78
3.32
3.92
3.34
2.93
3.53
3.01
2.64
3.53
3.01
2.64
t
DP
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
DIN
J
1.22
1.04
0.91
1.22
1.04
0.91
1.22
1.04
0.91
1.22
1.04
0.91
1.22
1.04
0.91
1.22
1.04
0.91
t
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
PY
t
EOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
R e v i s i o n 9
9.14
7.77
6.82
5.86
4.99
4.38
4.18
3.56
3.12
3.93
3.34
2.93
3.60
3.06
2.69
3.60
3.06
2.69
t
ZL
Table 2-6 on page 2-6
10.09
11.86
8.86
6.91
5.88
5.16
4.45
3.78
3.32
3.92
3.34
2.93
3.04
2.59
2.27
3.04
2.59
2.27
t
ZH
2.77
2.36
2.07
3.22
2.74
2.41
3.53
3.00
2.64
3.60
3.06
2.69
3.70
3.15
2.76
3.70
3.15
2.76
t
LZ
1.66
1.41
1.24
2.84
2.41
2.12
3.38
2.88
2.53
3.52
3.00
2.63
4.08
3.47
3.05
4.08
3.47
3.05
t
HZ
for derating values.
ProASIC3 Flash Family FPGAs
11.37
9.67
8.49
8.10
6.89
6.05
6.42
5.46
4.79
6.16
5.24
4.60
5.84
4.96
4.36
5.84
4.96
4.36
t
ZLS
14.10
11.99
10.53
t
9.15
7.78
6.83
6.68
5.69
4.99
6.16
5.24
4.60
5.28
4.49
3.94
5.28
4.49
3.94
ZHS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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