A3P125-PQG208 Actel, A3P125-PQG208 Datasheet - Page 96
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A3P125-PQG208
Manufacturer Part Number
A3P125-PQG208
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P125-PQG208
Processor Series
A3P125
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P125-PQG208
Manufacturer:
ACT
Quantity:
5
Part Number:
A3P125-PQG208
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P125-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3 DC and Switching Characteristics
Figure 2-22 • Output DDR Timing Diagram
Table 2-104 • Output DDR Propagation Delays
2- 82
Data_F
Data_R
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
CLK
CLR
Out
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
6
Commercial-Case Conditions: T
Timing Characteristics
t
DDROCLR2Q
1
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
t
J
Description
DDROSUD2
= 70°C, Worst-Case VCC = 1.425 V
8
3
2
R e visio n 9
t
DDROHD2
8
Table 2-6 on page 2-6
4
9
3
t
DDRORECCLR
9
0.70
0.38
0.38
0.00
0.00
0.80
0.00
0.22
0.22
0.36
0.32
TBD TBD TBD
–2
10
4
for derating values.
0.80
0.43
0.43
0.00
0.00
0.91
0.00
0.25
0.25
0.41
0.37
–1
5
Std.
0.94
0.51
0.51
0.00
0.00
1.07
0.00
0.30
0.30
0.48
0.43
10
Units
MHz
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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