A3P1000-FGG256 Actel, A3P1000-FGG256 Datasheet - Page 36

• Manufacturer Part Number: A3P1000-FGG256
• Description: FPGA - Field Programmable Gate Array 1M System Gates
• Manufacturer: Actel

Specifications of A3P1000-FGG256

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 300
• Data Ram Size: 147456
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1000 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 DC and Switching Characteristics
2- 22
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-22 • Summary of AC Measuring Points
Table 2-23 • I/O AC Parameter Definitions
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—High to Z
Enable to Pad delay through the Output Buffer—Z to High
Enable to Pad delay through the Output Buffer—Low to Z
Enable to Pad delay through the Output Buffer—Z to Low
Enable to Pad delay through the Output Buffer with delayed enable—Z to High
Enable to Pad delay through the Output Buffer with delayed enable—Z to Low
R e visio n 9
Parameter Definition
Measuring Trip Point (V
0.285 * VCCI (RR)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.615 * VCCI (FF)
0.90 V
0.75 V
1.4 V
1.4 V
1.2 V
trip
)