A3P1000-FGG256 Actel, A3P1000-FGG256 Datasheet - Page 37
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A3P1000-FGG256
Manufacturer Part Number
A3P1000-FGG256
Description
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P1000-FGG256
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
300
Data Ram Size
147456
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1000 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG256
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P1000-FGG256I
Manufacturer:
AC2
Quantity:
90
Company:
Part Number:
A3P1000-FGG256I
Manufacturer:
ACTEL
Quantity:
1
Company:
Part Number:
A3P1000-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG256I
Manufacturer:
MICROSEMI/美高森美
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Company:
Part Number:
A3P1000-FGG256T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
3.3 V LVCMOS
Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
LVDS
LVPECL
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
connectivity. This resistor is not required during normal operation.
–2 Speed Grade, Commercial-Case Conditions: T
Worst-Case V
Advanced I/O Banks
2
100 µA 12 mA High 35
12 mA 12 mA High 35
12 mA 12 mA High 35
12 mA 12 mA High 35
12 mA 12 mA High 35
PCI-X
24 mA
24 mA
spec
spec
PCI
Per
Per
CCI
–
–
–
–
(per standard)
High 10 25
High 10 25
High
High
–
–
– 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns
– 0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns
– 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns
– 0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns
– 0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns
– 0.45 1.37 0.03 1.20
– 0.45 1.34 0.03 1.05
4
4
0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
R e v i s i o n 9
J
= 70°C, Worst Case VCC = 1.425 V,
Table 2-6 on page 2-6
–
–
–
–
–
–
for derating values.
Figure 2-10 on page 2-66
ProASIC3 Flash Family FPGAs
–
–
–
–
–
–
–
–
2- 23
ns
ns
for