A54SX32A-PQG208 Actel, A54SX32A-PQG208 Datasheet - Page 43
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A54SX32A-PQG208
Manufacturer Part Number
A54SX32A-PQG208
Description
FPGA - Field Programmable Gate Array 48K System Gates
Manufacturer
Actel
Datasheet
1.A54SX08A-TQG100.pdf
(108 pages)
Specifications of A54SX32A-PQG208
Processor Series
A54SX32
Core
IP Core
Number Of Macrocells
1800
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
249
Delay Time
4 ns to 8.4 ns
Supply Voltage (max)
5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
2.25 V
Number Of Gates
32 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A54SX32A-PQG208
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
A54SX32A-PQG208
Manufacturer:
ACTEL
Quantity:
16
Company:
Part Number:
A54SX32A-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A54SX32A-PQG208
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A54SX32A-PQG208A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A54SX32A-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-18 • A54SX08A Timing Characteristics
Parameter
2.5 V LVCMOS Output Module Timing
t
t
t
t
t
t
t
t
d
d
d
Note:
1. Delays based on 35 pF loading.
2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V
DLH
DHL
DHLS
ENZL
ENZLS
ENZH
ENLZ
ENHZ
TLH
THL
THLS
Slew Rate [V/ns] = (0.1*V
where C
d
3
3
T[LH|HL|HLS]
3
load
(Worst-Case Commercial Conditions V
is the worst case delta value from the datasheet in ns/pF.
is the load capacitance driven by the I/O in pF
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low—low slew
Enable-to-Pad, Z to L
Data-to-Pad, Z to L—low slew
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta Low to High
Delta High to Low
Delta High to Low—low slew
CCI
Description
– 0.9*V
CCI)
/ (C
1,2
load
* d
T[LH|HL|HLS]
CCA
= 2.25 V, V
Min.
–2 Speed
)
v5.3
Max.
0.037
0.017
13.3
13.7
0.06
3.9
3.0
2.8
3.9
2.5
3.0
CCI
= 2.3 V, T
Min.
–1 Speed
J
Max.
0.043
0.023
0.071
= 70°C)
15.1
15.5
4.4
3.4
3.4
3.2
4.4
2.8
Min.
Std. Speed
CCI
value into the following equation:
Max.
0.051
0.023
0.086
18.2
17.7
5.2
3.9
3.7
5.2
3.3
3.9
Min.
–F Speed
SX-A Family FPGAs
Max.
0.071
0.037
0.117
25.5
24.8
7.2
5.5
5.2
7.2
4.7
5.5
Units
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
2-23