A3P400-FGG256 Actel, A3P400-FGG256 Datasheet - Page 9
A3P400-FGG256
Manufacturer Part Number
A3P400-FGG256
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-FGG256
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-FGG256C
Manufacturer:
ACTEL
Quantity:
1 156
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
YAGEO
Quantity:
460 000
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
ACT
Quantity:
1 170
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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*
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and
Not supported by A3P015 and A3P030 devices
† The A3P015 and A3P030 do not support PLL or SRAM.
Advanced Flash Technology
The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3 device consists of five distinct and programmable architectural features
Figure 1-2 on page
Decryption*
A3P125)
ISP AES
•
•
•
•
•
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs
Advanced I/O structure
1-4):
User Nonvolatile
FlashROM
Bank 0
Bank 1
†
†
R e v i s i o n 9
Charge Pumps
ProASIC3 Flash Family FPGAs
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
CCC
I/Os
VersaTile
(Figure 1-1
and
1 -3
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