A40MX02-PLG68 Actel, A40MX02-PLG68 Datasheet - Page 31

• Manufacturer Part Number: A40MX02-PLG68
• Description: FPGA - Field Programmable Gate Array 3K System Gates
• Manufacturer: Actel

Specifications of A40MX02-PLG68

• Processor Series: A40MX02
• Core: IP Core
• Number Of Macrocells: 295
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 57
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 3000
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter Measurement
Figure 1-21 • Output Buffer Delays
Figure 1-22 • AC Test Loads
Figure 1-23 • Input Buffer Delays
PAD
Y
GND
In
PAD
V
PAD
OL
t INYH
1.5V
(Used to measure propagation delay)
To the output under test
t DLH
50%
3V
INBUF
50%
1.5V
V
50%
1.5V
V
CCI
OH
t INYL
t DHL
Load 1
0V
Y
50%
1.5V
35 pF
E
PAD
D
TRIBUFF
t ENZL
50%
V
CCI
To the output under test
E
1.5V
50%
V
v6.1
OL
t ENLZ
Figure 1-24 • Module Delays
PAD
10%
(Used to measure rising/falling edges)
T o AC test loads (shown below)
S, A or B
V
C CI
Y
Y
E
PAD
GND
Load 2
R to V
R to GND for t PHZ/ t PZH
R=1k
GND
t PLH
t ENZH
50%
35 pF
50%
t PHL
50%
Ω
CCI
50%
50%
1.5V
50%
for t PLZ/ t PZL
V
40MX and 42MX FPGA Families
OH
PHL
t ENHZ
t PLH
S
A
B
50%
90%
50%
Y
1-25