A40MX02-PLG68 Actel, A40MX02-PLG68 Datasheet - Page 51

• Manufacturer Part Number: A40MX02-PLG68
• Description: FPGA - Field Programmable Gate Array 3K System Gates
• Manufacturer: Actel

Specifications of A40MX02-PLG68

• Processor Series: A40MX02
• Core: IP Core
• Number Of Macrocells: 295
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 57
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 3000
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 31 •
Parameter Description
Logic Module Propagation Delays
t
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
Input Module Propagation Delays
t
t
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
4. Delays based on 35 pF loading.
PD1
PD2
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
MAX
INYH
INYL
3
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX04 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
Single Module
Dual-Module Macros
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch)
Asynchronous Pulse Width
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock Frequency
(FO = 128)
Pad-to-Y HIGH
Pad-to-Y LOW
2
1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
4.3
0.0
4.3
0.0
4.6
4.6
6.8
CC
109
1.7
3.7
1.7
1.7
1.7
1.9
2.7
3.4
4.1
7.1
1.0
0.9
= 3.0V, T
v6.1
‘–2’ Speed
5.0
0.0
5.0
0.0
5.3
5.3
7.8
J
= 70°C)
101
8.1
2.0
4.3
2.0
2.0
2.0
2.2
3.1
3.9
4.8
1.1
1.0
‘–1’ Speed
5.6
0.0
5.6
0.0
5.6
5.6
8.9
2.3
4.9
2.3
2.3
2.3
2.5
3.5
4.4
5.4
9.2
1.3
1.1
92
‘Std’ Speed
10.4
6.6
0.0
6.6
0.0
7.0
7.0
40MX and 42MX FPGA Families
10.9
2.7
5.7
2.7
2.7
2.7
3.0
4.1
5.2
6.3
1.5
1.3
80
14.6
‘–F’ Speed
9.2
0.0
9.2
0.0
9.8
9.8
15.2
3.7
8.0
3.7
3.7
3.7
4.2
5.7
7.3
8.9
2.1
1.9
48
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-45