PT7C4311WEX Pericom Semiconductor, PT7C4311WEX Datasheet - Page 9

• Manufacturer Part Number: PT7C4311WEX
• Description: IC REAL TIME CLK/CALENDAR 8-SOIC
• Manufacturer: Pericom Semiconductor
• Type: Clock/Calendarr

Specifications of PT7C4311WEX

• Memory Size: 56B
• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PT7C4311WEXTR

|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
c)
START condition, repeated START condition, and STOP condition
•
•
•
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
d)
•
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note: with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
PT0322(08/09)
START condition
STOP condition
Repeated START condition (RESTART condition)
Starting and Stopping I
Data Transfers and Acknowledge Responses during I
Data transfers
SDA level changes from low to high while SCL is at high level
SDA level changes from high to low while SCL is at high level
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
2
C Bus Communications
Fig.2 Starting and stopping on I
2
C-BUS Communication
9
2
C bus
Real-time Clock Module (I
Data Sheet
PT7C4311
2
C Bus)
Ver: 2