MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet
MSC8144VT800A
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MSC8144VT800A Summary of contents
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... QUICC Engine™ technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three communication controllers with one ATM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores. © 2007–2010 Freescale Semiconductor, Inc. Document Number: MSC8144 MSC8144 FC-PBGA–783 29 mm × – ...
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... Figure 36.SPI AC Timing in Master Mode (Internal Clock Figure 37.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . . 62 Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63 with Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 63 DDIO Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 42 DDM3 Figure 44.MSC8144 Mechanical Information, 783-ball FC-PBGA Package and V Power-on Sequence . . . . . 65 DDM3IO 25M3 Freescale Semiconductor ...
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... Instruction Cache OCE30 DPU P-bus SC3400 Xa-bus Core Xb-bus Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor 10 Mbytes M3 Memory Controller 128-bit at 400 MHz CLASS QUICC Engine Subsystem Serial RapidIO Subsystem ...
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... FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown MSC8144 Figure 3. MSC8144 FC-PBGA Package, Top View MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Figure 3 and Figure 4 Top View with their ball location index numbers Freescale Semiconductor ...
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... Figure 4. MSC8144 FC-PBGA Package, Bottom View MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Bottom View ...
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... PCI Ethernet GND GND PCI Ethernet 2 V PCI Ethernet GND Freescale Semiconductor Ref. GND DDGE2 DDGE2 DDGE2 DDGE2 DDSXC — — — — DDSXC DDSXC DDSXC DDSXC DDSXC RIOPLL SXC DDSXC DDSXC DDSXC DDSXC DDSXP DDDDR DDDDR DDDDR DDDDR DDDDR — ...
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... C18 Reserved C19 V DDSXP C20 SRIO_TXD2/GE1_SGMII_T X MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) SGMII support on SERDES is enabled by Reset Configuration Word SGMII support on SERDES is enabled by Reset Configuration Word Ethernet 2 TDM ...
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... UTOPIA V Ethernet 2 UTOPIA V UTOPIA Ethernet 1 UTOPIA V Ethernet 2 UTOPIA V GND V GND V V GND V GND V GND Freescale Semiconductor Ref. DDSXP DDSXP DDSXP DDDDR DDDDR DDDDR GND DDDDR — DDGE2 GND DDGE2 DDGE2 DDGE1 DDGE2 — — — — SXP DDSXP SXP DDSXP DDSXC — ...
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... DDGE1 F4 GE1_TD3/UTP_TD5/ PCI_AD30 F5 GE1_TD1/UTP_TD3/ PCI_AD28 F6 GND F7 GE1_TD0/UTP_TD2/ PCI_AD27 F8 V DDGE1 F9 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 ...
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... UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA Ethernet 1 PCI — (100) 5 (101) 6 (110) 7 (111) UTOPIA Ethernet 1 UTOPIA UTOPIA Ethernet 1 UTOPIA UTOPIA Ethernet 1 UTOPIA UTOPIA Ethernet 1 UTOPIA Freescale Semiconductor Ref. Supply V DD GND V DD GND V DD GND V DD GND V DD GND V DD — V ...
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... J1 Reserved J2 GND J3 V DDIO J4 STOP_BS 4 J5 NMI_OUT 4 J6 INT_OUT SDA/GPIO27 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UART/GPIO/IRQ GPIO/ Ethernet PCI IRQ 1 PCI Ethernet 1 I2C/GPIO 2 4 (100) 5 (101) ...
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... DDDDR MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) 2 Supply 4 (100) 5 (101) 6 (110) 7 (111 Freescale Semiconductor Ref. V DDIO V DD GND V DD GND V DD GND GND GND V DD GND V DD GND GND GND ...
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... DDDDR L28 MCK1 1 M1 Reserved M2 TRST M3 EE0 M4 EE1 M5 UTP_RCLK/PCI_AD13 M6 UTP_RADDR0/PCI_AD7 M7 UTP_TD8/PCI_AD30 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA TMR/ UTOPIA GPIO TIMER/GPIO TIMER/GPIO I UART/GPIO/IRQ UTOPIA PCI UTOPIA PCI ...
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... UTOPIA PCI Power UTOPIA PCI UTOPIA PCI TIMER/GPIO 2 Supply 4 (100) 5 (101) 6 (110) 7 (111 UTOPIA UTOPIA UTOPIA PCI TIMER/GPIO UTOPIA Freescale Semiconductor Ref. V DDIO V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD DDDDR DDDDR DDDDR DDDDR ...
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... GND P28 MCK2 1 R1 Reserved R2 TCK R3 TDO R4 UTP_RD12/PCI_AD16 R5 UTP_RCLAV_PDRPA/ PCI_AD12 R6 UTP_RADDR4/PCI_AD11 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI GPIO/IRQ PCI GPIO/IRQ PCI UTOPIA ...
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... PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI GPIO/IRQ PCI 2 4 (100) 5 (101) 6 (110) 7 (111) PCI UTOPIA UTOPIA UTOPIA UTOPIA PCI GPIO/IRQ Freescale Semiconductor Ref. Supply V DDIO V DDIO GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... U28 MDQ0 1 V1 Reserved V2 UTP_TD10/PCI_CBE0 V3 UTP_TADDR3 V4 UTP_TD1/PCI_PERR V5 UTP_TADDR0/PCI_AD23 V6 UTP_TADDR1/PCI_AD24 V7 UTP_TCLAV/PCI_AD28 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI ...
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... UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI UTOPIA PCI 2 Supply 4 (100) 5 (101) 6 (110) 7 (111 UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA Freescale Semiconductor Ref. V DDIO V DDIO GND V DDM3 GND V DDM3 GND V DDM3 GND V DDM3 GND V DDM3 GND GND DDDDR DDDDR DDDDR DDDDR ...
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... UTP_TD13/PCI_CBE3 AA3 TDM5RSYN/PCI_AD15 GPIO10 AA4 TDM5TDAT, AT/PCI_AD17/ 6 GPIO11 AA5 TDM5RCLK/PCI_AD13 GPIO28 AA6 GND MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA PCI TDM/GPIO TDM TDM TDM UTOPIA PCI UTOPIA ...
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... TDM 2 4 (100) 5 (101) 6 (110) 7 (111) PCI TDM PCI TDM UTOPIA PCI TDM/GPIO/ IRQ PCI TDM/GPIO PCI TDM/GPIO/IRQ PCI TDM/GPIO/IRQ PCI TDM PCI TDM Freescale Semiconductor Ref. Supply V DDIO V DDIO V DDIO V DDM3 GND V DDM3 GND V DDM3 GND V DDM3 GND V DDM3 GND ...
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... AC26 MECC0 AC27 V DDDDR AC28 ECC_MDQS 1 AD1 Reserved 3, 6 AD2 GPIO1 AD3 TMR0/GPIO13 MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) UTOPIA UTOPIA TDM TDM/GPIO/IRQ TDM/GPIO/IRQ TDM PCI TIMER/GPIO 2 4 (100) ...
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... GPIO GPIO/IRQ/SPI 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM TDM TDM GPIO GPIO TDM TDM TDM TDM TDM TDM TDM Freescale Semiconductor Ref. Supply V DDIO GND V DDIO V DDIO V DDIO V DDIO GND V 25M3 GND V DDM3 GND V 25M3 GND ...
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... V DDDDR AF27 GND AF28 V DDDDR 1 AG1 Reserved 3, 6 AG2 GPIO16/IRQ0 AG3 TDM0TCLK MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) GPIO/IRQ/SPI GPIO/IRQ 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM TDM ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev I/O Multiplexing Mode On 0 (000) 1 (001) 2 (010) 3 (011) GPIO/IRQ/SPI GPIO/IRQ/SPI 2 4 (100) 5 (101) 6 (110) 7 (111) TDM TDM TDM TDM TDM TDM Freescale Semiconductor Ref. Supply V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO — GND ...
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... For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register programming. See Chapter 23, GPIO of the MSC8144 Reference Manual for configuration details. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor I/O Multiplexing Mode On ...
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... INGE1 V DDGE2 V INGE2 V DDIO V INIO Value Unit –0.3 to 1.1 V –0.3 to 1.1 V –0.3 to 1.32 V –0.3 to 2.75 V –0.3 to 1.98 V –0.3 to 0.51 × DDDDR –0 0.3 V DDDDR –0.3 to 3.465 V –0 0.3 V DDGE1 –0.3 to 3.465 V –0 0.3 V DDGE2 –0.3 to 3.465 V –0 0.3 V DDIO Freescale Semiconductor ...
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... Operating temperature range: • Standard (VT) • Intermediate (SVT) • Extended (TVT) Note: PLL supply voltage is specified at input of the filter and not at pin of the MSC8144 (see MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 2. Absolute Maximum Ratings Symbol V DDM3IO V 25M3 ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 4. Output Drive Impedance Output Impedance (Ω) Symbol Natural Convection R 20 θ θJA R θJB R 0.8 θ (half strength mode) FC-PBGA × Unit 200 ft/min (1 m/s) airflow 15 °C/W 12 °C/W 7 °C/W °C/W Freescale Semiconductor ...
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... It is the supply to which far end signal termination is made and is expected equal This rail should track variations in the DC level of V REF 4. Output leakage is measured with all outputs are disabled MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor (typ) = 2.5 V and DDR2 SDRAM uses V Symbol Min V DDDDR 0.49 × ...
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... DDDDR Min Max 2.3 2.7 0.51 × V DDDDR DDDDR – 0. 0.04 REF + 0. 0.3 DDDDR –0.3 MV – 0.15 REF –50 50 –16.2 — 16.2 — DC variations as measured at the receiver. . ≤ DDDDR REF Min Max — 500 MVREF Freescale Semiconductor Unit μ Unit μA ...
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... SRIO_REF_CLK Figure 5. SerDes Reference Clocks Input Stage MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor . The reference clock must be able to drive this termination. The GND SXC SXC allows compatibility with HCSL type reference clocks specified for PCI-Express ...
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... V DDPCI 0.7 × V DDPCI μA –30 30 μA –30 30 μA –30 30 μA –30 30 0.9 × V — V DDPCI 0.1 × V — V DDPCI 10 pF Min Max Unit 3.135 3.465 V 2.0 3.465 V –0.3 0.8 V μA –30 30 μA –30 30 2.4 — V — 0.4 V Freescale Semiconductor ...
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... Input leakage current supply voltage IN Output high voltage – Output low voltage Input Pin Capacitance Note: 1. Not tested. Guaranteed by design. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Electrical Characteristics Symbol Min Max V 3.135 3.465 DDGE1 V DDGE2 V 2.0 3.465 ...
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... C, IRQn, NMI_OUT, INT_OUT, Min Max 3.135 3.465 2.0 3.465 –0.3 0.8 –30 30 –30 30 –30 30 –30 30 2.4 3.465 — 0.4 Freescale Semiconductor Unit μA μA μ Unit V V μ Unit μA μA μA μ ...
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... CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded. Characteristic CLKIN frequency PCI_CLK_IN frequency CLKIN duty cycle PCI_CLK_IN duty cycle MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor reaches its nominal value. DDIO range during V power-up., so their amplitude grows as V DDIO DDIO ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Table 17 Table 17. Reset Sources Description Power-On Reset Hard Reset (HRESET) (PORESET) External or Internal External only (Software Watchdog, Software or RapidIO) Yes No Yes No Yes No Yes No describes the reset sources. Soft Reset (SRESET) External or JTAG Command: internal EXTEST, CLAMP, or Software HIGHZ Freescale Semiconductor ...
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... MHz <= CLKIN < 66 MHz • 66 MHz <= CLKIN < 100 MHz • 100 MHz <= CLKIN < 133 MHz MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Power-On Reset Hard Reset (HRESET) (PORESET) External or Internal External only (Software Watchdog, Software or RapidIO) ...
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... Reset configuration write sequence during this period. Expression Max Min 15369/CLKIN 615 233 34825/CLKIN 528 262 92545/CLKIN 3702 2103 107435/CLKIN 2441 1627 124208/CLKIN 1882 1242 157880/CLKIN 1579 1187 16/CLKIN 640 120 3 Freescale Semiconductor Unit μs μs μs μs μs μs ns ...
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... MDQS[n] and any corresponding bit that is CISKEW captured with MDQS[n]. Subtract this value from the total timing budget recommended operating conditions with V MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Symbol 2.5 ± ...
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... MCK MCK –0.6 0.6 memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH follows the DDKHMP Freescale Semiconductor Unit ...
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... MCK[n] MCK[n] MDQS MDQS Figure 9 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor to skew measurement (t MCK MDQS t MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 8. Timing for t DDKHMH ...
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... Differential Peak-Peak = 2 × (A – Transmitter or Receiver DDDDR Comments 8 ns applies only to serial RapidIO system with 125-MHz reference clock. 6.4 ns applies only to serial RapidIO systems with a 156.25 MHz reference clock. Note: SGMII uses the 8 ns (125 MHz) value only. Freescale Semiconductor ...
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... GB, and 3.125 GB. Table 25. Short Run Transmitter AC Timing Specifications—1.25 GBaud Characteristic Output Voltage Differential Output Voltage Deterministic Jitter Total Jitter MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor , is defined defined as V – The differential output signal ranges between 500 mV ...
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... Voltage relative to COMMON of either signal comprising a differential pair Skew at the transmitter output between lanes of a multilane link ±100 ppm Notes Voltage relative to COMMON of either signal comprising a differential pair Skew at the transmitter output between lanes of a multilane link ±100 ppm Freescale Semiconductor ...
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... The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Range Symbol Unit ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev 1-B Time min (mV) V max (mV) DIFF DIFF 250 500 400 800 250 500 400 800 250 500 400 800 1 (UI) B (UI) 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 Freescale Semiconductor ...
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... Differential Input Voltage Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Multiple Input Skew Bit Error Rate Unit Interval MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Range Symbol Unit Min Max V 200 1600 ...
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... Figure 13. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Skew at the receiver input between lanes of a multilane link ±100 ppm 1.875 MHz 20 MHz Freescale Semiconductor ...
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... Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test methods. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 34) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) A ...
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... PCOFF t 7.0 — PCSU t 0 — PCH –12 . The eye pattern ± 5% differential to 2.5 GHz. and Table 35. Note that for this to occur, provides the PCI AC timing specifications. 66 MHz Unit Min Max 1.0 6.0 ns 1.0 — ns — 3.0 — — ns Freescale Semiconductor ...
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... Figure 16. PCI Input AC Timing Measurement Conditions Figure 17 shows the PCI output AC timing conditions. Output Delay High-Impedance Output Figure 17. PCI Output AC Timing Measurement Condition MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor 33 MHz Symbol Min Max of the rising edge of PCI_CLK_IN to 0.4 × V DDIO Table 19 ...
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... Figure 18. TDM Inputs Signals t TDMXKH Figure 19. TDMxTSYN in TSO=0 mode Expression Min Max — (0.5 ± 0.1) × — (0.5 ± 0.1) × — 3.6 — 1.9 — 2.5 — — 9.8 2.5 — — 9.8 — 9.25 2.0 — TDMCL Freescale Semiconductor Units ...
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... guaranteed by design. UREFCLK REFCLK Figure 21 shows the UART input AC timing UTXD, URXD inputs Figure 22 shows the UART output AC timing UTXD output MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor t TDMC t t TDMCH TDMCL t TDMDHOV t TDMDHOX t TDMSHOV Figure 20. TDM Output Signals Table 38 ...
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... TMREFCLK T T TMCL TMCH Figure 23. Timer Timing Symbol t MDKHDX t MDDVKH t MDDXKH ) to a maximum value of 2.5 MHz (400 ns period for t MDC Symbol Min Unit T 10.0 ns TMREFCLK T 4.0 ns TMCH T 4.0 ns TMCL Min Max Unit — — The value depends on the MDC Freescale Semiconductor ...
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... RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK Notes: 1. Typical RX_CLK period (t MRX 2. Program GCR4 as 0x00030CC3. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor t MDC t t MDDVKH MDDXKH t MDKHDX ) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns. ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Ω Figure 26. AC Test Load Valid Data t MRDVKH t Figure 27. MII Receive AC Timing ) RMX V /2 DDGE = 50 Ω MRDXKH 1 Symbol Min Max RMXH/ RMX RMTKHDX t 4.0 — RMRDVKH t 2.0 — RMRDXKH Freescale Semiconductor Unit % ...
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... Notes: 1. Typical REF_CLK clock period is 8ns 2. Measured using load. 3. Measured using load 4. Program GCR4 as 0x00002008 Figure 30 shows the SMII Mode signal timing. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor t RMX t t RMXF RMXH t RMTKHDX Valid Data t RMRDVKH = 50 Ω ...
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... Valid Figure 30. SMII Mode Signal Timing of 2.5 V +/- 5 2.5 V +/- 5%. DD Valid Symbol Min Typ Max t -0.5 — 0.5 SKEWT t 0.9 — 2.6 SKEWR Symbol Min Typ Max t –2.6 — –0.9 SKEWT t –0.5 — 0.5 SKEWR Freescale Semiconductor Unit ns ns Unit ns ns ...
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... TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At DSP) Figure 31. RGMII AC Timing and Multiplexing MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor t SKEWT TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXD[9] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] ...
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... ATM/UTOPIA/UTOPIA timing with external clock. CLK (input) t UEIVKH Input Signals: Output Signals: Figure 33. ATM/UTOPIAPOS AC Timing (External Clock) MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Symbol Min t 1 UEKHOV t 1 UEKHOX t 4 UEIVKH t 1 UEIXKH = 50 Ω Ω UEIXKH t UEKHOV t UEKHOX Max Unit Freescale Semiconductor ...
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... Note) Note: The clock edge is selectable on SPI. Figure 35. SPI AC Timing in Slave Mode (External Clock) Figure 36 shows the SPI timings in master mode (internal clock). MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 48. SPI AC Timing Specifications Symbol t NIKHOV t ...
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... Input Output MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev NIIXKH t NIIVKH t NIKHOX t NIKHOV Table 49. Signal Timing Symbol Type t Asynchronous IN t Asynchronous OUT t OUT Figure 37. Asynchronous Signal Timing Min One CLKIN cycle Application dependent t IN Freescale Semiconductor 1 ...
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... Figure 39 shows the boundary scan (JTAG) timing diagram. TCK (Input) Data Inputs Data Outputs Data Outputs MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 50. JTAG Timing t TCKX V M Figure 38. Test Clock Input Timing t BSVKH Input Data Valid t ...
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... MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev TDIVKH Input Data Valid t TDOHOV Output Data Valid t TDOHOZ Figure 40. Test Access Port Timing Figure 41. TRST Timing power rail with extremely low impedance path TDIXKH and V supplies. DDM3 DDSXC DDSXP Freescale Semiconductor ...
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... If the M3 memory is not used the RapidIO interface is not used, V 3.1.2 Start-Up Timing Section 2.6.1 describes the start-up timing. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor should be either at same time or after V REF I/O supplies V V DDM3 and V ...
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... The filter Ω resistor in series with two 2.2 μF, DDPLL inputs. These traces should be short and direct. DDPLL 10 Ω V DDPLL0 2.2 μF 10 Ω V DDPLL0 2.2 μF 10 Ω V DDPLL0 2.2 μF Figure 43. PLL Supplies Figure 43). For optimal noise filtering, place MSC8144 Freescale Semiconductor ...
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... Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used Signal Name MDQ[0–31] MDQS[0–3] MDQS[0–3] MA[0–15] MCK[0–2] MCK[0–2] MCS[0–1] MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 51. Hardware Design Considerations Pin Connection ...
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... MDIC[0–1] MRAS MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin Connection GND GND Pin connection in use pull- DDDDR in use pull-down to GND in use pull- DDDDR in use in use in use in use in use NC in use in use in use in use in use in use Freescale Semiconductor ...
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... SRIO_TXD[0–3] V DDRIOPLL GND RIOPLL GND SXP GND SXC V DDSXP V DDSXC MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Hardware Design Considerations Pin connection in use 1/2*V DDDDR 2 1.8 V Table 53 to determine Pin connection pull- DDDDR NC pull-down to GND pull- ...
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... Table 56. Connectivity of M3 Related Pins When M3 Memory Is Not Used Signal Name M3_RESET V 25M3 V DDM3 V DDM3IO MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin Connection in use in use in use in use GND SXC GND SXC use in use GND SXP GND SXC 1.0 V 1.0 V Pin Connection NC GND GND GND Freescale Semiconductor ...
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... Table 58. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required Signal Name GE1_COL GE1_CRS GE1_RD[0–3] GE1_RX_ER GE1_RX_CLK GE1_RX_DV GE1_SGMII_RX GE1_SGMII_RX GE1_SGMII_TX MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Hardware Design Considerations is DDGE1 Pin Connection GND ...
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... Table 60. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required Signal Name GE2_RD[0-3] GE2_RX_CLK GE2_RX_DV GE2_RX_ER GE2_SGMII_RX MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev Pin Connection NC NC GND tied DDGE2 Pin Connection GND SXC GND SXC Pin Connection GND GND GND GND GND SXC Freescale Semiconductor ...
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... UTP_TCLAV UTP_TCLK UTP_TD[0–15] UTP_TEN UTP_TPRTY UTP_TSOC V DDIO MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor lists the recommended management pin connections. Table 62 assumes that the alternate function of the specified pin is Hardware Design Considerations Pin Connection GND SXC NC ...
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... Pin Connection GND GND GND GND GND GND 3.3 V Table 64 assumes that the alternate function of the Pin Connection GND GND GND V DDIO V DDIO V DDIO GND V DDIO GND V DDIO NC V DDIO V DDIO V DDIO 3.3 V Freescale Semiconductor Table 63 ...
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... When using I/O multiplexing mode tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND. Note: For details on configuration, see the MSC8144 Reference Manual. For additional information, refer to the MSC8144 Design Checklist (AN3202). MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Hardware Design Considerations Table 65 assumes that the alternate Pin Connection ...
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... Lead-free 0M31H 1.0 V 1M31H 1.0 V Core Operating Frequency Order Number Temperature (MHz) 0° to 90°C 800 MSC8144VT800A 0° to 105°C 800 MSC8144SVT800A –40° to 105°C 800 MSC8144TVT800A 0° to 90°C 1000 MSC8144VT1000A 0° to 105°C 1000 MSC8144SVT1000A –40° to 105°C ...
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... MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and registers. MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor CASE NO. 1842-04 Package Information Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M– ...
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... Changed t value. TDMSHOX Figure 27 and Figure 30. DDGE Table Table 55. Table 13, Table 14, Table in Table 45 from ns. MDDVKH Table 45. Figure 3 and Figure 4. Table 1. Table 1. Table 1. 52. Table 71. Table 8, Table 10, Section 2.7.4.1, Section 2.7.4.2, 10. Table 18. 51. 11, Table 16, Table 17, Table 18, and Table 19 Freescale Semiconductor Table 56. ...
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... Updated orderable part numbers to Section 4. 15 Nov 2009 • Updated Core and PLL input voltage tolerance in 16 May 2010 • Corrected typo in MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Description to 1.213 (1.25 – 3%) in DDM3 Figure 34. Table 20 in Section 2.7.2. ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...