MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 37

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MSC8144VT800A

Manufacturer Part Number
MSC8144VT800A
Description
IC DSP QUAD 800MHZ 783FCBGA
Manufacturer
Freescale Semiconductor
Series
MSC81xx StarCorer
Type
SC3400 Corer
Datasheet

Specifications of MSC8144VT800A

Interface
Ethernet, I²C, SPI, TDM, UART, UTOPIA
Clock Rate
800MHz
Non-volatile Memory
External
On-chip Ram
10.5MB
Voltage - I/o
3.30V
Voltage - Core
1.00V
Operating Temperature
0°C ~ 90°C
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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2.6.3.1
Asserting
V
2.6.3.2
The MSC8144 has two mechanisms for writing the reset configuration:
Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the
Reset Word Configuration Source and operating conditions:
The
and is also sampled during power-on reset sequence for RCW loading from an I
2.6.3.3 Reset Timing Tables
Table 19
Freescale Semiconductor
HRESET driven
IPBus modules reset (TDM, UART, SWT,
DDRC, IPBus master, GIC, HS, and GPIO)
SRESET driven
Extended cores reset
CLASS registers reset
Timers, Performance Monitor
QUICC Engine subsystem, PCI, DMA
DD
No.
1
RCFG_CLKIN_RNG
and
Reset Action/Reset Source
V
Through the I
Through external pins
Through internal hard coded
RCW_SRC[2–0]
RC[16–0]
and
Required external PORESET duration minimum
PORESET
DDIO
33 MHz <= CLKIN < 44 MHz
44 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN < 100 MHz
100 MHz <= CLKIN < 133 MHz
Figure 7
are both at their nominal levels.
Power-On Reset (PORESET) Pin
Reset Configuration
initiates the power-on reset flow.
describe the reset timing for a reset configuration.
2
C port
pin must be valid during power-on or hard reset sequence. The
Table 18. Reset Actions for Each Reset Source (continued)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Table 19. Timing for a Reset Configuration Write
Characteristics
Power-On Reset
External only
(PORESET)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PORESET
Hard Reset (HRESET)
(Software Watchdog,
Software or RapidIO)
External or Internal
must be asserted externally for at least 32
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
C EEPROM.
Expression
32/CLKIN
External or
Software
registers
registers
internal
STOP_BS
Some
Most
Yes
Yes
Yes
No
No
Soft Reset (SRESET)
Electrical Characteristics
pin must be always valid
Max
1280
728
485
320
Depends on command
EXTEST, CLAMP, or
JTAG Command:
Some registers
Most registers
CLKIN
HIGHZ
Min
Yes
Yes
727
484
320
241
No
No
cycles after
Unit
ns
ns
ns
ns
37

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