MSC8144SVT1000A Freescale Semiconductor, MSC8144SVT1000A Datasheet - Page 79

• Manufacturer Part Number: MSC8144SVT1000A
• Description: IC DSP QUAD 1GHZ 783FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144SVT1000A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 1.0GHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Rev.
10
12
13
14
15
16
11
7
8
9
May 2010
Dec 2007
Dec 2007
Mar 2008
Aug 2008
Aug 2008
Feb 2009
Nov 2009
Apr 2008
Jul 2009
Date
• Changed minimum voltage level for V
• Added POS to titles in Section 2.6.6.
• Added additional signals to titles in Section 2.6.8. Added high and low voltage ranges to
• Added ATM and POS to headings in Section 2.7.11. Changed characteristics to generic input/output in
• Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13, Asynchronous Signal Timing. Renumbered
• Added POS to all UTOPIA references in Section 3.4.5.
• Changed GCR4 program value to 0x0004C130 in Note 7 in
• Changed description of
• Added
• Changed the first sentence in Section 3.4.8 to reflect that Table 70 indicates what to do with pins if they are
• Updated ordering information in Section 4.
• Multiple corrections of minor punctuation errors.
• Removed the comment about preliminary estimates before
• Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables renumbered.
• Changed units for I
• Removed signal low and high input current from
• Added a note to
• Changed minimum clock frequency to 33 MHz and maximum clock frequency to 133 MHz in
• Deleted old Table 17 Clock Parameters.
• Changed minimum input clock frequency to 33 MHz in
• Changed the t
• Removed t
• Removed t
• Removed t
• The parameters t
• The parameters t
• The parameters t
• The parameters t
• Removed the parameters t
• Changed t
• Updated
• Removed TCK rise and fall time from
• Updated orderable part numbers in Section 4.
• Changed b8t to bit in the M3 memory description on the first page.
• Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of
• Changed packet processor to QUICC Engine Subsystem in the last row of
• In
• Updated package drawing to the latest revision, Case No. 1842-04 in
• Updated MV
• Updated orderable part numbers to Section 4.
• Updated Core and PLL input voltage tolerance in
• Corrected typo in
Figure
subsequent sections, tables, and figures.
“not” required by the design. Changed the Pin Connection for GPIO[0–31] to GND.
associated figure.
or tested.
required or tested.
required or tested.
required or tested.
required or tested.
t
DSP).
G125H
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Figure
/t
33, and
3
G125
Table 66. Document Revision History (continued)
to the PLL supply voltage row in Table 2.
Figure 35
31, for GTX_CLK, changed (at transmitter) to (at DSP) and for RX_CLK, changed (at PHY) to (at
UEKHOX
PCRSTCLK
REFPJ
UAVKH
were removed from
REF
DDKHAX
Figure
Table 15
MTXH
MRXH
RMXH
MDCH
and t
equations and temperature ranges in
Table
and t
OH
to guaranteed by design in
and
, t
REFCJ
34.
/t
/t
/t
PCRSTOFF
, t
and I
minimum value in
UAVXH
Figure 36
Table 20
MTX
MRX
RMX
23. Changed MCLK minimum time to 5 ns.
MDCR
to exclude TDM and TMS. Removed reference to overshoot and undershoot and
RGT
OL
, t
from
, t
, t
, t
MTXR
MRXR
RMXR
, and t
from
to mA in
RGTH
, t
in Section 2.7.2.
Table 45
Table 24
SPI timing diagrams.
PCRST
, and t
, and t
, and t
Table 38
MDHF
/t
RGT
DDM3
Table
, and t
Table
MTXF
MRXF
RMXF
Table 23
and
(1000Base-T), t
because the specifications are not required or tested.
were removed from
to 1.213 (1.25 – 3%) in
50.
PCRHFA
because the specifications are not required or tested.
Table
Description
9.
Table 46
were removed from
were removed from
were removed from
Table
Table
to 1.85 ns.
47.
from
Table
12.
because the specifications are not required or tested.
3.
Table
RGTH
Table 4
Table 36
Table
3.
19.
Table 40
/t
RGT
51.
and removed non-DDR rows in the table.
Table 41
Table 42
Table 43
because the specifications are not required
Table
(10Base-T), t
Figure
because the specifications are not
Table
3.
44.
because the specifications are not
because the specifications are not
because the specifications are not
Table
18.
RGTR
14.
, t
Table
RGTF
Revision History
, t
Table
19.
G12
, and
Table
16.
52,
79