PIC16LF1526-I/MR Microchip Technology, PIC16LF1526-I/MR Datasheet - Page 280
![MCU PIC 14KB FLASH 64QFN](/photos/16/3/160367/tqfp-64_sml.jpg)
PIC16LF1526-I/MR
Manufacturer Part Number
PIC16LF1526-I/MR
Description
MCU PIC 14KB FLASH 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1526T-IPT.pdf
(354 pages)
Specifications of PIC16LF1526-I/MR
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C
Maximum Clock Frequency
20 MHz
Number Of Timers
ÿ6 x 8-bit, 3 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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PIC16(L)F1526/27
FIGURE 22-12:
TABLE 22-8:
DS41458A-page 280
BAUD1CON
BAUD2CON
INTCON
PIE1
PIE4
PIR1
PIR4
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
Legend:
TXx/CKx pin
TXx/CKx pin
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
RXx/DTx
RCxIF bit
SREN bit
CREN bit
RCxREG
bit SREN
Name
Write to
Read
pin
*
Page provides register information.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
‘0’
TMR1GIE
TMR1GIF
ABDOVF
ABDOVF
CCP10IE
CCP10IF
CSRC
CSRC
SPEN
SPEN
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
GIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
CCP9IE
CCP9IF
RCIDL
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
RX9
TX9
TX9
bit 1
TMR0IE
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, High Byte
EUSART1 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, Low Byte
RC1IE
RC2IE
RC1IF
RC2IF
SREN
SREN
TXEN
TXEN
Bit 5
—
—
EUSART1 Receive Register
EUSART2 Receive Register
bit 2
Preliminary
TX1IE
TX2IE
CREN
CREN
SYNC
SYNC
SCKP
SCKP
TX1IF
TX2IF
INTE
Bit 4
bit 3
CCP8IE
SSP1IE
CCP8IF
ADDEN
ADDEN
SSP1IF
SENDB
SENDB
BRG16
BRG16
IOCIE
Bit 3
bit 4
TMR0IF
CCP1IE
CCP7IE
CCP1IF
CCP7IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
bit 5
TMR2IE
TMR2IF
BCL2IE
BCL2IF
OERR
OERR
TRMT
TRMT
WUE
WUE
INTF
Bit 1
2011 Microchip Technology Inc.
bit 6
bit 7
TMR1IE
SSP2IE
TMR1IF
ABDEN
ABDEN
SSP2IF
IOCIF
RX9D
RX9D
TX9D
TX9D
Bit 0
Register
on Page
260*
260*
267*
267*
267*
267*
266
266
265
265
264
264
93
94
97
98
97
‘0’
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