STM32F101ZGT6 STMicroelectronics, STM32F101ZGT6 Datasheet - Page 63

IC ARM CORTEX 1MB 144LQFP

STM32F101ZGT6

Manufacturer Part Number
STM32F101ZGT6
Description
IC ARM CORTEX 1MB 144LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101ZGT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
112
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Processor Series
STM32F101xG
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
80 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
112
Number Of Timers
15
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Processor To Be Evaluated
STM32F101ZG
Supply Current (max)
28 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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STM32F101xF, STM32F101xG
Synchronous waveforms and timings
Figure 25
Table 38
with the following FSMC configuration:
Figure 25. Synchronous multiplexed NOR/PSRAM read timings
FSMC_AD[15:0]
FSMC_A[25:16]
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NADV
FSMC_NOE
FSMC_CLK
FSMC_NEx
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
t d(CLKL-NADVL)
t d(CLKL-ADV)
provide the corresponding timings. The results shown in these tables are obtained
through
t w(CLK)
Figure 28
t d(CLKL-ADIV)
t d(CLKL-NExL)
t d(CLKL-AV)
AD[15:0]
represent synchronous waveforms and
Doc ID 17143 Rev 2
t su(NWAITV-CLKH)
t su(NWAITV-CLKH)
t d(CLKL-NADVH)
t su(ADV-CLKH)
Data latency = 1
t w(CLK)
t su(NWAITV-CLKH)
t d(CLKL-NOEL)
D1
t su(ADV-CLKH)
t h(CLKH-ADV)
t h(CLKH-NWAITV)
t h(CLKH-NWAITV)
t d(CLKH-NOEH)
t d(CLKH-NExH)
t d(CLKH-AIV)
Electrical characteristics
t h(CLKH-NWAITV)
D2
Table 36
BUSTURN = 0
t h(CLKH-ADV)
through
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