MC56F8255VLD Freescale Semiconductor, MC56F8255VLD Datasheet - Page 47

• Manufacturer Part Number: MC56F8255VLD
• Description: DSC 64K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8255VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

word ensures that the device remains secure after the next reset (caused, for example, by the device powering down). Refer to
the flash memory section of the device’s reference manual for details.
When flash security mode is enabled, the MC56F825x/MC56F824x disables the core’s EOnCE debug capabilities. Normal
program execution is otherwise unaffected.
6.2
Several methods effectively lock or unlock the on-chip flash.
6.2.1
You can read on-chip flash by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The
TCK, TMS, TDO, and TDI pins compose a JTAG interface onto which the EOnCE port functionality is mapped. When the
device boots, the chip-level JTAG port is active and provides the chip’s boundary scan capability and access to the ID register.
However, proper implementation of flash security blocks any attempt to access the internal flash memory via the EOnCE port
when security is enabled. This protection is effective when the device comes out of reset, even prior to the execution of any
code at startup.
6.2.2
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the
configuration field. The erasure disables security by clearing the protection register. This approach does not compromise
security. The entire contents of your secured code stored in flash are erased before the next reset or power-up sequence, when
security becomes disabled.
To start the lockout recovery sequence via JTAG, first shift the JTAG public instruction (LOCKOUT_RECOVERY) into the
chip-level TAP controller’s instruction register. Then shift the clock divider value into the corresponding 7-bit data register.
Finally, the TAP controller must enter the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must
remain in this state until the erase sequence is complete. Refer to the device’s reference manual for details, or contact Freescale.
6.2.3
You can use CodeWarrior to unlock a device by selecting the following items in the indicated sequence:
You can accomplish the same task with another CodeWarrior mechanism that uses the device’s memory configuration file: the
command “Unlock_Flash_on_Connect 1” in the .cfg file.
This lockout recovery mechanism completely erases the internal flash contents, including the configuration field, thereby
disabling security (the protection register is cleared).
Freescale Semiconductor
1.
2.
3.
Debug menu
DSP56800E
Unlock Flash
Flash Access Lock and Unlock Mechanisms
Disabling EOnCE Access
Flash Lockout Recovery Using JTAG
Flash Lockout Recovery Using CodeWarrior
After completion of the lockout recovery sequence, you must reset the JTAG TAP
controller and the device to return to normal unsecured operation. A power-on reset resets
both.
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
NOTE
Security Features
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