MC56F8255VLD Freescale Semiconductor, MC56F8255VLD Datasheet - Page 58

• Manufacturer Part Number: MC56F8255VLD
• Description: DSC 64K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8255VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Specifications
7.14
58
1
2
3
4
5
Accumulated jitter using an 8 MHz external crystal as the PLL source
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
The core system clock operates at 1/6 of the PLL output frequency.
This is the time required after the PLL is enabled to ensure reliable operation.
From powerdown to powerup state at 60 MHz system clock state.
This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 60 MHz system clock
frequency and using an 8 MHz oscillator frequency.
1
2
3
4
5
Input high voltage overdrive by an external clock
Input high voltage overdrive by an external clock
Parameters listed are guaranteed by design.
See
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
External
Clock
Phase Locked Loop Timing
Figure 17
Note: The midpoint is V
External clock input rise time
External clock input fall time
PLL input reference frequency
Table 29. External Clock Operation Timing Requirements
for details on using the recommended connection of an external clock driver.
Characteristic
10%
50%
90%
PLL output frequency
Cycle-to-cycle jitter
PLL lock time
Characteristic
t
PW
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
IL
+ (V
Table 30. Phase Locked Loop Timing
3 4
Figure 17. External Clock Timing
IH
5
4
– V
2
IL
t
)/2.
1
PW
Symbol
t
t
V
rise
V
fall
ih
il
5
0.85V
Min
—
—
—
Symbol
t
fall
t
jitterpll
DD
t
f
f
J
plls
ref
op
A
Typ
—
—
—
—
1
Min
120
—
—
—
4
(continued)
t
rise
0.3V
Typ
350
40
Max
—
—
Freescale Semiconductor
8
—
3
3
DD
10%
50%
90%
Max
TBD
240
100
—
8
V
V
Unit
IH
ns
ns
V
V
IL
Unit
MHz
MHz
µs
ps
%