MCIMX515DVK8C Freescale Semiconductor, MCIMX515DVK8C Datasheet - Page 106
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MCIMX515DVK8C
Manufacturer Part Number
MCIMX515DVK8C
Description
IC MPU I.MX51 527MABGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheets
1.MCIMX512DJM8C.pdf
(200 pages)
2.MCIMX515DJM8C.pdf
(2 pages)
3.MCIMX515DVK8C.pdf
(156 pages)
Specifications of MCIMX515DVK8C
Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
800MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
257-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX515DVK8C
Manufacturer:
FREESCALE
Quantity:
66
Company:
Part Number:
MCIMX515DVK8C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX515DVK8C-M77X
Manufacturer:
FREESCALE
Quantity:
20 000
Electrical Characteristics
9
DISP_UP is predefined in REGISTER
10
DISP_DOWN is predefined in REGISTER
11
DISP_UP is predefined in REGISTER
12
13
Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data
14
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
4.7.8.8
The IPU supports the following types of asynchronous serial interfaces:
The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire
interfaces.
Figure 63
active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal.
For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
106
Display control up for read
Display control up for write
Display control down for read
This parameter is a requirement to the display connected to the IPU
Data read point
Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
1. 3-wire (with bidirectional data line).
2. 4-wire (with separate data input and output lines).
3. 5-wire type 1 (with sampling RS by the serial clock).
4. 5-wire type 2 (with sampling RS by the chip select signal).
depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to
Standard Serial Interfaces
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Tdicdrw
Tdicuw
Tdicur
Tdrp
=
=
=
=
1
-- - T
2
1
-- - T DI_CLK
2
1
-- - T DI_CLK
2
T
⎛
⎝
⎛
⎝
⎛
⎝
DI_CLK
DI_CLK
×
×
×
ceil
×
ceil
ceil
ceil
DISP#_READ_EN
------------------------------------------------ -
DI_CLK_PERIOD
2
---------------------------------------------------- -
---------------------------------------------- -
DI_CLK_PERIOD
---------------------------------------------- -
DI_CLK_PERIOD
2
DI_CLK_PERIOD
2
×
×
×
DISP_DOWN_#
DISP_UP_#
DISP_UP_#
⎞
⎠
⎞
⎠
⎞
⎠
Freescale Semiconductor