MCIMX515DVK8C Freescale Semiconductor, MCIMX515DVK8C Datasheet - Page 94
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX515DVK8C
Manufacturer Part Number
MCIMX515DVK8C
Description
IC MPU I.MX51 527MABGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheets
1.MCIMX512DJM8C.pdf
(200 pages)
2.MCIMX515DJM8C.pdf
(2 pages)
3.MCIMX515DVK8C.pdf
(156 pages)
Specifications of MCIMX515DVK8C
Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
800MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
257-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX515DVK8C
Manufacturer:
FREESCALE
Quantity:
66
Company:
Part Number:
MCIMX515DVK8C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX515DVK8C-M77X
Manufacturer:
FREESCALE
Quantity:
20 000
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Electrical Characteristics
4.7.8.6
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in
94
2
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Display interface clock down time
Display interface clock up time
Interface to a TV Encoder
•
•
•
•
•
•
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles
—
of VSYNC and HSYNC coincide.
—
coincide.
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
At a transition to an odd field (of the next frame), the negative edges
At a transition is to an even field (of the same frame), they do not
Figure
Tdicd
Tdicu
56.
=
=
1
-- - T diclk
2
⎛
⎝
1
-- - T diclk
2
⎛
⎝
×
ceil
×
NOTE
ceil
2
------------------------------------------------------------ -
×
2
-------------------------------------------------- -
DI_CLK_PERIOD
DI_CLK_PERIOD
DISP_CLK_DOWN
×
DISP_CLK_UP
⎞
⎠
⎞
⎠
Freescale Semiconductor
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