MCZ33905BS3EK Freescale Semiconductor, MCZ33905BS3EK Datasheet - Page 38

• Manufacturer Part Number: MCZ33905BS3EK
• Description: IC SBC CAN HS 3.3V 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905BS3EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and conditions to enter or leave each mode are illustrated in
the state diagram.
INIT RESET
“powered on”. In this mode, the RST pin is asserted low, for
a duration of typically 1.0 ms. Control bits and flags are “set”
to their default reset condition. The BATFAIL is set to indicate
the device is coming from an unpowered condition, and all
previous device configurations are lost and “reset” the default
value. The duration of the INIT reset is typically 1.0 ms.
expected SPI command does not occur in due time (Ref. INIT
Mode), and if the device is not in the debug mode.
INIT
Mode. In this mode, the device must be configured via SPI
within a time of 256 ms max.
and INIT MISC must be, and can only be configured during
INIT Mode.
Watchdog Refresh command must be sent in order to set the
device into Normal Mode. If the SPI watchdog refresh does
not occur within the 256 ms period, the device will return into
INIT Reset Mode for typically 1.0 ms, and then re enter into
INIT Mode.
device status or to read back the INIT register configuration.
command, it is only possible to re-enter the INIT Mode using
a secured SPI command. In INIT Mode, the CAN, LIN1, LIN2,
VAUX, I/O_x and Analog MUX functions are not operating.
The 5 V-CAN is also not operating, except if the Debug Mode
is detected.
RESET
entered from Normal Mode, Normal Request Mode, LP V
on Mode and from the Flash Mode when the watchdog is not
triggered, or if a V
can define a longer Reset pulse activation only when the
Reset Mode is entered following a V
pulse is always 1.0 ms, when reset mode is entered due to
wrong watchdog refresh command.
command.
NORMAL REQUEST
after a Wake-Up from LP V
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FUNCTIONAL DEVICE OPERATION
MODE AND STATE DESCRIPTION
The device has several operation modes. The transitions
This mode is automatically entered after the device is
INIT reset mode is also entered from INIT Mode if the
This mode is automatically entered from the INIT Reset
Four registers called INIT Wdog, INIT REG, INIT LIN I/O
Other registers can be written in this and other modes.
Once the INIT register configuration is done, a SPI
Register read operation is allowed in INIT Mode to collect
When INIT Mode is left by a SPI watchdog refresh
In this mode, the RST pin is asserted low. Reset Mode is
The duration of reset is typically 1.0 ms by default. You
Reset Mode can be entered via the secured SPI
This mode is automatically entered after RESET Mode, or
DD
low condition is detected.
DD
ON Mode.
DD
FUNCTIONAL DEVICE OPERATION
low condition. Reset
MODE AND STATE DESCRIPTION
DD
transition to NORMAL Mode. The duration of the Normal
request mode is 256 ms when Normal Request Mode is
entered after RESET Mode. Different durations can be
selected by SPI when normal request is entered from LP V
ON Mode.
within the 256 ms (or the shorter user defined time out), then
the device will enter into RESET Mode for a duration of
typically 1.0 ms.
well as in LP Modes, the V
NORMAL
is entered by a SPI watchdog refresh command from Normal
Request Mode, or from INIT Mode.
operating, and a periodic watchdog refresh must occur.
When an incorrect or missing watchdog refresh command is
initiated, the device will enter into Reset Mode.
(LP V
Dedicated, secured SPI commands must be used to enter
from Normal Mode to Reset Mode, INIT Mode or Flash Mode.
FLASH
to typically 32 seconds. This allow programming of the MCU
flash memory while minimizing the software over head to
refresh the watchdog. The flash mode is entered by Secured
SPI command and is left by SPI command. Device will enter
into Reset Mode. When an incorrect or missing watchdog
refresh command device will enter into Reset Mode. An
interrupt can be generated at 50% of the watchdog period.
CAN bus, inside the vehicle.
DEBUG
allows for easy software and hardware debugging. The
debug operation is detected after power up if the DBG pin is
set to 8.0 to 10 V range.
operations are disabled: 256 ms of INIT Mode, watchdog
refresh of Normal Mode and Flash Mode, Normal Request
time out (256 ms or user defined value) are not operating and
will not lead to transition into INIT reset or Reset Mode.
be sent without any time constraints with respect to the
watchdog operation and the MCU program can be “halted” or
“paused” to verify proper operation.
A watchdog refresh SPI command is necessary to
If the watchdog refresh SPI command does not occur
Note: in init reset, init, reset and normal request modes as
In this mode, all device functions are available. This mode
During Normal Mode, the device watchdog function is
While in Normal Mode, the device can be set to LP Modes
In this mode, the software watchdog period is extended up
CAN interface operates in Flash Mode to allow flash via
Debug is a special operation mode of the device which
When debug is detected, all the software watchdog
When the device is in Debug Mode, the SPI command can
DD
ON or LP V
DD
Analog Integrated Circuit Device Data
OFF) using the SPI command.
DD
external PNP is disabled.
Freescale Semiconductor
DD