LM25066APSQE/NOPB National Semiconductor, LM25066APSQE/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM25066APSQE/NOPB
• Description: IC CTLR PM HOTSWAP 24-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM25066APSQE/NOPB

• Applications: Base Station-Networking Line Cards, Servers
• Current - Supply: 5.8mA
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Input Voltage: 17V
• Internal Switch: No
• Supply Voltage Range: 2.9V To 5.5V
• Rohs Compliant: Yes
• Digital Ic Case Style: LLP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25066APSQE/NOPBTR

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Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate. During normal oper-
ating conditions (t
by an internal 22 µA current source. The voltage at the GATE
pin (with respect to ground) is limited by an internal 18.8 V
zener diode. See the graph “GATE Pin Voltage” provided
previously. Since the gate-to-source voltage applied to Q
could be as high as 18.8 V during various conditions, a zener
diode with the appropriate voltage rating must be added be-
tween the GATE and OUT pins if the maximum V
the selected MOSFET is less than 18.8 V. The external zener
diode must have a forward current rating of at least 190 mA.
When the system voltage is initially applied, the GATE pin is
held low by a 190 mA pull-down current. This helps prevent
an inadvertent turn-on of the MOSFET through its drain-gate
capacitance as the applied system voltage increases.
During the insertion time (t
low by a 2 mA pull-down current. This maintains Q
state until the end of t
UVLO. Following the insertion time, during t
gate voltage of Q
dissipation level from exceeding the programmed levels.
While in the current or power limiting mode, the TIMER pin
capacitor is charging. If the current and power limiting cease
1
3
in
is controlled to keep the current or power
Figure
1
, regardless of the voltage at VIN or
1
in
2), the gate of Q
Figure
FIGURE 2. Power Up Sequence (Current Limit Only)
2), the GATE pin is held
2
1
in
is held charged
Figure
GS
1
in the off-
rating of
2, the
1
14
before the TIMER pin reaches 1.7V, the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If
the inrush limiting condition persists such that the TIMER pin
reached 1.7V during t
190 mA pull-down current. The GATE pin is then held low until
either a power up sequence is initiated (RETRY pin to VDD)
or an automatic retry is attempted (RETRY pin to GROUND).
See the Fault Timer & Restart section. If the system input
voltage falls below the UVLO threshold or rises above the
OVLO threshold, the GATE pin is pulled low by the 2 mA pull-
down current to switch off Q
Current Limit
The current limit threshold is reached when the voltage across
the sense resistor R
voltage limit of 25 mV or 46 mV depending on whether the CL
pin is connected to GND or VDD, respectively. In the current
limiting condition, the GATE voltage is controlled to limit the
current in MOSFET Q
the fault timer is active as described in the Fault Timer &
Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the
LM25066A resumes normal operation. If the current limit con-
dition persists for longer than the Fault Timeout Period set by
the timer capacitor, C
S
2
1
, the GATE pin is then pulled low by the
. While the current limit circuit is active,
(VIN to SENSE) exceeds the internal
T
, the IIN OC FAULT bit in the
1
.
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