LP8720TLX-B/NOPB National Semiconductor, LP8720TLX-B/NOPB Datasheet
LP8720TLX-B/NOPB
Specifications of LP8720TLX-B/NOPB
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LP8720TLX-B/NOPB Summary of contents
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... SMD 20–bump package. Applications ■ Cellular Handsets ■ Portable hand-held products Typical Application Diagram © 2009 National Semiconductor Corporation LP8720 Features ■ 5 Low Noise LDO’s for up to 300 mA ■ One high-efficiency Synchronous Magnetic Buck Regulator, I ...
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... Package Marking Information Ordering Information Order Number LP8720TLE LP8720TLX Upon request there will be available custom versions – customer can order own default voltages and own startup sequence. For more information please contact local National Semiconductor Corp. sales office. www.national.com TOP VIEW ...
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LP8720 Pin Descriptions Pin Number Name Type A4 VBATT P E4 VINB P A2 VIN1 P D1 VIN2 P B4 LDO1 A A3 LDO2 A A1 LDO3 A C1 LDO4 A E1 LDO5 ...
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Device Description OPERATION MODES POWER-ON-RESET: After VBATT gets above POR higher threshold DEFSEL-pin and IDSEL-pin are read. Then all internal registers of LP8720 are reset to the default values and after that LP8720 goes to STANDBY mode. This process duration ...
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POWER-ON AND POWER-OFF SEQUENCES Start Up Sequence if DEFSEL=VBATT or DEFSEL=Hi-Z t 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. BON t 25 µs – time step. Time step accuracy is defined by OSC ...
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Reference and bias turn ON. Min 100 µs max 200 µs. BON t 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. S Note 1 START UP and SHUT DOWN sequences ...
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Start Up Sequence DEFSEL Start Up Sequence VBATT LDO1 enable same time. LDO5 and BUCK enable via Serial Interface. GND LDO3 enable. LDO1 and BUCK enable via Serial Interface . Hi-Z LDO1 ...
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www.national.com 8 ...
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Register 0x00 EXT_DVS_CONTROL 1 – DVS-pin control: DVS=HI then BUCK_V1[4:0] DVS=LO then BUCK_V2[4:0] 0 – Serial interface control: DVS_V2/V1=1 then BUCK_V1[4:0] DVS_V2/V1=0 then BUCK_V2[4:0] EXT_SLEEP_CONTROL 1 – DVS-pin control: DVS=HI then normal DVS=LO then SLEEP 0 – Serial interface control: ...
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Register 0x08 LDO1_EN LDO2_EN In STANDBY mode LDO3_EN LDO4_EN 1 – During next START UP sequence will be enabled. LDO5_EN BUCK_EN 0 – During next START UP sequence will be NOT enabled. For proper operation output having “111 NO start ...
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Support Functions REFERENCE LP8720 has internal reference block creating all necessary references and biasing for all blocks. OSCILLATOR There is internal oscillator giving clock to the bucks and to logic control. V =3.6V BATT Parameter Typ Min Oscillator 2.0 1.9 ...
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... Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications VINB, VBATT BATT VIN1, VIN2 -0. All other pins -0. Junction Temperature (TJ-MAX) Storage Temperature Maximum Continuous Power Dissipation P (Note 3) D-MAX ESD ...
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Logic and Control Unless otherwise noted VBATT VINB values and limits appearing in normal type apply for T temperature range for operation -40 to +125°C. J Symbol Parameter Logic and Control Inputs VIL Input Low Level ...
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Buck Converter Unless otherwise noted VBATT VINB values and limits appearing in normal type apply for T temperature range for operation Symbol Parameter V Feedback Voltage FB V Output Voltage, PWM Mode 3.0V BUCK V Output ...
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Output Voltage Selection Using External Resistor Divider Buck1 output voltage can be programmed via the selection of the external feedback resistor network. V will be adjusted to make the voltage at FB equal to 0.5V. OUT The resistor from FB ...
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LDO’s There are all together 5 LDO’s in LP8720 grouped as A-type LDO’s (LDO 2,3) D-type LDO’s (LDO 1,5) LO-type LDO (LDO4) The A-type LDO’s are optimized for supplying of analog loads and have ultra low noise (15 µVRMS) and ...
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A-Type LDO Electrical Characteristics Unless otherwise noted VBATT VINB values and limits appearing in normal type apply for T temperature range for operation -40 to +125°C. J Symbol Parameter V Output Voltage Accuracy OUT I Output ...
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Serial Interface Unless otherwise noted VBATT VINB values and limits appearing in normal type apply for T temperature range for operation Symbol Parameter f Clock Frequency CLK t Bus-Free Time between START BF and STOP t ...
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I 2 C-Compatible Serial Bus Interface INTERFACE BUS OVERVIEW The compatible synchronous serial interface provides ac- cess to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional com- munications between ...
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AFTER EVERY BYTE” RULE The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the “acknowledge after every byte” rule. When the master ...
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REGISTER READ AND WRITE DETAIL FIGURE 4. Register Write Format FIGURE 5. Register Read Format 21 30067529 30067530 www.national.com ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted Micro SMD 20 Package NS Package Number MKT-TLA2011A X1 = 1.970 mm ±0.030 2.466 mm ±0.030 0.600 mm ±0.075 mm 22 ...
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Notes 23 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...