ISL9305IRTHWCLBZ-T Intersil, ISL9305IRTHWCLBZ-T Datasheet
ISL9305IRTHWCLBZ-T
Specifications of ISL9305IRTHWCLBZ-T
Related parts for ISL9305IRTHWCLBZ-T
ISL9305IRTHWCLBZ-T Summary of contents
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... FIGURE 1. TYPICAL APPLICATION DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 2 C-Bus Series Interface Transfers the Control Data ...
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PARTS DESCRIPTION MANUFACTURER L1, L2 Inductor Sumida C1 Input capacitor Murata C2, C3 Intput capacitor Murata C4, C5 Output capacitor Murata C6, C7 Output capacitor Murata R1, R2, Resistor Various R3, R4 Pin Configuration Pin Descriptions PIN NUMBER (TQFN) NAME ...
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Pin Descriptions (Continued) PIN NUMBER (TQFN) NAME 11 FB2 Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For fixed output versions, connect this pin directly to the DCD2 output. 12 VINDCD2 Input ...
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... Ordering Information PART NUMBER PART (Notes MARKING ISL9305IRTHAANLZ-T 9305I HAANLZ ISL9305IRTHWBNLZ-T 9305I HWBNLZ ISL9305IRTHWCLBZ-T 9305I HWCLBZ ISL9305IRTHWCNYZ-T 9305I HWCNYZ ISL9305IRTHWCNLZ-T 9305I HWCNLZ ISL9305IRTHWLNCZ-T 9305I HWLNCZ ISL9305IRTHBCNLZ-T 9305I HBCNLZ ISL9305IRTHBFNCZ-T 9305I HBFNCZ NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range .-40°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VINDCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V VINDCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to VINDCD1 VINLDO1 and VINLDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to VINDCD1 DCD1 and DCD2 Output Current ...
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Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: T LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no ...
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Theory of Operation DCD1 and DCD2 Introduction Both the DCD1 and DCD2 converters on ISL9305H use the peak-current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Both converters are able to supply up to 1.5A ...
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Undervoltage Lockout (UVLO) An undervoltage lockout (UVLO) circuit is provided on ISL9305H. The UVLO circuit block can prevent abnormal operation in the event that the supply voltage is too low to guarantee proper operation. The UVLO on VINDCD1 is set ...
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S SLAVE ADDRESS 0 A REGISTER ADDRESS R/W OPTIONAL DATA BYTE 2 A AUTO INCREMENT REGISTER ADDRESS S SLAVE ADDRESS 0 A REGISTER ADDRESS R/W DATA BYTE 1 A DATA BYTE 2 AUTO INCREMENT REGISTER ADDRESS FIGURE ...
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I C Control Registers All the registers are reset at initial start-up. DCD OUTPUT VOLTAGE CONTROL REGISTER DCD1OUT, address 0x00h; DCD2OUT, address 0x01h Caution: Disable DCD prior to changing from fixed output voltage to adjustable output voltage or from ...
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LDO1 AND LDO2 OUTPUT VOLTAGE CONTROL REGISTERS LDO1OUT, address 0x02h and LDO2OUT, address 0x03h. LDOOUT LDO OUTPUT <7:0> VOLTAGE (V) 00 0.9 01 0.95 02 1.00 03 1.05 04 1.1 05 1.15 06 1.20 07 1.25 08 1.30 09 1.35 ...
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DCD1 AND DCD2 CONTROL REGISTER DCD_PARAMETER, address 0x04h TABLE 6. DCD_PARAMETER REGISTER BIT NAME ACCESS RESET DCD_PHASE R/W 0 DCD1 and DCD2 PWM switch selection. 0-in phase 180° out-of-phase. B5 DCD2_ULTRA R/W 0 ...
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Typical Operating Conditions FIGURE 8. DCD OUTPUT RIPPLE (V = 4.2V, PFM, TIME SCALE = 1µs) IN CH1: VODCD1 (20mV/DIV), CH2: IL1 (500mA/DIV), CH3: VODCD2 (20mV/DIV), CH4: IL2 (500mA/DIV) FIGURE 10. INDUCTOR CURRENT RIPPLE (V TIME SCALE = 200ns) CH1: ...
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Typical Operating Conditions FIGURE 14. 4-CHANNEL DEFAULT START- LOAD CH1: VODCD1 (2V/DIV), CH2: VODCD2 (1V/DIV), CH3: VOLDO1 (1V/DIV), CH4: VOLDO2 (2V/DIV) 100 5. 3. ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing L16.4x4G 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/10 4.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN ...