ISL9305IRTHWCNYZ-T Intersil, ISL9305IRTHWCNYZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL9305IRTHWCNYZ-T
• Description: IC PMIC 800MA 3MHZ 16TQFN
• Manufacturer: Intersil

Specifications of ISL9305IRTHWCNYZ-T

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 3: 0.9 V ~ 3.3 V, 350mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
DCD1 and DCD2 Introduction
Both the DCD1 and DCD2 converters on ISL9305H use the
peak-current-mode pulse-width modulation (PWM) control scheme
for fast transient response and pulse-by-pulse current limiting.
Both converters are able to supply up to 1.5A load current. The
default output voltage ranges from 0.8V to 3.6V depending on the
factory pre-set configuration and can be programmed via the I
interface in the range of 0.825V to 3.6V at 25mV/step with a
programmable slew rate. An open-drain DCDPG (DCD Power-Good)
signal is also provided to monitor the DCD1 and DCD2 output
voltages. Optionally, both DCD1 and DCD2 can be programmed to
be actively discharged via an on-chip bleeding resistor (typical
115Ω) when the converter is disabled.
Skip Mode (PFM Mode) for DCD1/DCD2
Under light load condition, the DCD1 and DCD2 can be programmed
to automatically enter a pulse-skipping mode to minimize the
switching loss by reducing the switching frequency. Figure 3
illustrates the skip mode operation. A zero-cross sensing circuit
monitors the current flowing through SW node for zero crossing.
When it is detected to cross zero for 16 consecutive cycles, the
regulator enters the skip mode. During the 16 consecutive cycles,
the inductor current could be negative. The counter is reset to zero
when the sensed current flowing through SW node does not cross
zero during any cycle within the 16 consecutive cycles. Once the
converter enters the skip mode, the pulse modulation is controlled
by an internal comparator while each pulse cycle remains
synchronized to the PWM clock. The P-Channel MOSFET is turned on
at the rising edge of the clock and turned off when its current
reaches ~20% of the peak current limit. As the average inductor
current in each cycle is higher than the average current of the load,
the output voltage rises cycle-over-cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the P-Channel
MOSFET is turned off immediately and the inductor current is fully
discharged to zero and stays at zero. The output voltage reduces
gradually due to the load current discharging the output capacitor.
When the output voltage drops to the nominal voltage, the P-
Channel MOSFET will be turned on again, repeating the previous
operations.
CLOCK
V
OUT
I
L
0
7
16 CYCLES
FIGURE 3. SKIP MODE OPERATION WAVEFORMS
20% PEAK CURRENT LIMIT
ISL9305H
1.015*V
2
C
OUT_NOMINAL
V
OUT_NOMINAL
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Soft-Start
The soft-start reduces the in-rush current during the start-up stage.
The soft-start block limits the current rising speed so that the
output voltage rises in a controlled fashion.
Overcurrent Protection
The overcurrent protection for DCD1 and DCD2 is provided on
ISL9305H for when an overload condition occurs. When the current
at P-Channel MOSFET is sensed to reach the current limit, the
internal protection circuit is triggered to turn off the P-Channel
MOSFET immediately.
DCD Short-Circuit Protection
The ISL9305H provides Short-Circuit Protection for both DCD1 and
DCD2. The feedback voltage is monitored for output short-circuit
protection. When the output voltage is sensed to be lower than a
certain threshold, the internal circuit will change the PWM oscillator
frequency to a lower frequencies in order to protect the IC from
damage. The P-Channel MOSFET peak current limit remains active
during this state.
v
v
EAMP
v
OUT
CSA
d
i
L
FIGURE 2. PWM OPERATION WAVEFORMS
November 8, 2010
FN7724.0