ISL9305IRTHWLNCZ-T Intersil, ISL9305IRTHWLNCZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL9305IRTHWLNCZ-T
• Description: IC PMIC 800MA 3MHZ 16TQFN
• Manufacturer: Intersil

Specifications of ISL9305IRTHWLNCZ-T

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 3: 0.9 V ~ 3.3 V, 350mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DCD1 AND DCD2 CONTROL REGISTER
DCD_PARAMETER, address 0x04h
SYSTEM CONTROL REGISTER
SYS_PARAMETER, address 0x05h
BIT
BIT
B7
B6 DCD_PHASE
B5 DCD2_ULTRA
B4 DCD1_ULTRA
B3
B2
B1 DCD2_MODE
B0 DCD1_MODE
B7
B6
B5 DCDPOR_1
B4 DCDPOR_0
B3 LDO2_EN
B2 LDO1_EN
B1 DCD2_EN
B0 DCD1_EN
DCD2_BLD
DCD1_BLD
I
NAME
2
NAME
C_EN
-
-
TABLE 6. DCD_PARAMETER REGISTER
TABLE 7. SYS_PARAMETER REGISTER
ACCESS RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ACCESS RESET
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
0
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
12
Reserved
I
1-enabled
DCDPG Delay Time Setting,
DCDPG[1:0]:
00 to 1ms
01 to 50ms
10 to 150ms
11 to 200m
LDO2 enable selection. 0-disable,
1-enable.
LDO1 enable selection. 0-disable,
1-enable
DCD2 enable selection. 0-disable,
1-enable.
DCD2 enable selection. 0-disable,
1-enable
2
C function enable. 0-disabled;
DCD1 and DCD2 PWM switch
selection. 0-in phase; 1 to 180°
out-of-phase.
Ultrasonic feature under PFM mode
for DCD2. 0-disabled; 1-enabled.
Ultrasonic feature under PFM mode
for DCD1. 0-disabled; 1-enabled.
Selection of DCD2 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
Selection of DCD1 for active output
voltage discharge when disabled.
0-disabled; 1-enabled.
Selection on DCD2 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
Selection on DCD1 of auto
PFM/PWM mode (= 1) or forced
PWM mode (= 0).
DESCRIPTION
DESCRIPTION
Reserved
ISL9305H
DCD OUTPUT VOLTAGE SLEW RATE CONTROL
REGISTER
DCD_SRCTL, address 0x06h
BIT
B7 DCD2SR_2
B6 DCD2SR_1
B5 DCD2SR_0
B4
B3 DCD1SR_2
B2 DCD1SR_1
B1 DCD1SR_0
B0
TABLE 8. DCD OUPUT VOLTAGE SLEW RATE CONTROL
Reserve
Reserve
NAME
ACCESS RESET
R/W
R/W
R/W
R/W
R/W
R/W
-
-
0
0
1
0
0
0
1
0
REGISTER
DCD2 Slew Rate Setting, DCD2SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to immediate
Reserved
DCD1 Slew Rate Setting, DCD1SR[2:0]:
000 to 0.225mV/µs
001 to 0.45mV/µs
010 to 0.90mV/µs
011 to 1.8mV/µs
100 to 3.6mV/µs
101 to 7.2mV/µs
110 to 14.4mV/µs
111 to immediate
Reserved
DESCRIPTION
November 8, 2010
FN7724.0