ISL6324ACRZ-T Intersil, ISL6324ACRZ-T Datasheet
ISL6324ACRZ-T
Specifications of ISL6324ACRZ-T
Related parts for ISL6324ACRZ-T
ISL6324ACRZ-T Summary of contents
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... Ordering Information PART NUMBER PART (Note) MARKING ISL6324ACRZ* ISL6324A CRZ ISL6324AIRZ* ISL6324A IRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, ...
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Pinout FB_NB ISEN_NB+ SDA VID0/VFIXEN VID1/SEL VID2/SVD VID3/SVC VID4 VID5 VCC RGND 12 Integrated Driver Block Diagram PWM SOFT-START AND CONTROL FAULT LOGIC 2 ISL6324A ISL6324A ISL6324A HYBRID SVI AND PVI (48 LD QFN) TOP VIEW 48 ...
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Controller Block Diagram SCL CORE_OVP DAC_OFS SDA ISEN_NB+ CURRENT SENSE ISEN_NB- VDDPWRGD APA APA COMP VDDPWRGD_MOD FB E/A DVC 2X ∑ RGND PWROK VID0/VFIXEN SVI VID1/SEL SLAVE BUS VID2/SVD DAC_OFS AND VID3/SVC PVI DAC VID4 VID5 NB_REF ...
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Typical Application - SVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 UGATE2 FS PHASE2 LGATE2 RSET VFIXEN ISEN2- SEL ISEN2+ SVD SVC RGND VID4 NC NC VID5 PWROK ...
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Typical Application - PVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 UGATE2 FS PHASE2 LGATE2 RSET VID0 ISEN2- VID1/SEL ISEN2+ VID2 VID3 RGND VID4 VID5 NC PWROK ISEN4+ ...
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... Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below BOOT-PHASE - 0. 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6324ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6324AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS high VCC high PVCC1_2 high PVCC_NB ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. PARAMETER System Accuracy (0.600V < VDAC < 1.000V) System Accuracy (VDAC < 0.600V) DVC Voltage Gain APA Current Tolerance ERROR AMPLIFIER DC Gain Gain-Bandwidth Product (Note 3) Slew Rate ...
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Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified. PARAMETER UGATE Turn-On Non-overlap LGATE Turn-On Non-overlap GATE DRIVE RESISTANCE (Note 3) Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance MODE ...
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Functional Pin Description VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6324A. If the pin is LO prior to enable, the ISL6324A is in SVI mode and the ...
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... MOSFETs’ gates. PWM3 and PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable them and configure the core VR controller for 2-phase or 3-phase operation ...
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Operation The ISL6324A utilizes a multi-phase architecture to provide a low cost, space saving power conversion solution for the processor core voltage. The controller also implements a simple single phase architecture to provide the Northbridge voltage on the same chip. ...
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... FS pin and ground. The advantage of Intersil’s proprietary Active Pulse Positioning (APP) modulator is that the PWM signal has the ability to turn on at any point during this PWM time interval, and turn off immediately after the PWM signal has transitioned high ...
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FS pin and ground. The PWM signals command the MOSFET driver to turn on/off the channel MOSFETs. For 4-channel operation, the channel firing order is 1-2-3-4: PWM3 pulse happens 1 ...
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... Channel-current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current balance method is illustrated in Figure 6, with error correction for Channel 1 represented. In the figure, the cycle ...
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TABLE 1. 6-BIT PARALLEL VID CODES (Continued) VID5 VID4 VID3 VID2 VID1 ...
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VCC SVC SVD ENABLE PWROK VDD AND VDDNB VDDPWRGD VFIXEN FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP PRE-PWROK METAL VID Typical motherboard start-up occurs with the VFIXEN input low. The controller decodes the SVC ...
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VID values. Details of the SVI Bus protocol are provided in the AMD Design Guide for Voltage Regulator Controllers Accepting Serial VID Codes specification. Once the set VID command is received, the ISL6324A decodes the information to determine ...
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... The integrating compensation network shown in Figure 8 insures that the steady-state error in the output voltage is limited only to the error in the reference voltage, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6324A to include the combined tolerances of each of these elements. The output of the error amplifier, V modulator to generate the PWM signals ...
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The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. ...
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... VCC ISL6324A becomes enabled. The schematic in Figure 10 demonstrates sequencing the ISL6324A with the ISL66xx PVCC1_2 family of Intersil MOSFET drivers, which require 12V bias. PVCC_NB When selecting the value of the resistor divider the driver +12V maximum rising POR threshold should be used for calculating the proper resistor values. This will prevent 10.7kΩ ...
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Phase Detection The ISEN3- and ISEN4- pins are monitored prior to soft-start to determine the number of active CORE channel phases. If ISEN4- is tied to VCC, the controller will configure the channel firing order and timing for 3-phase operation. ...
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REPEAT FOR EACH 12.5µA - CORE CHANNEL OCP + ONLY SOFT-START, FAULT AND CONTROL LOGIC DUPLICATED FOR + NB AND CORE 1.8V OVP - + DAC + 250mV VSEN UV + DAC - 300mV ...
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Sampling” on page 13 and “Channel-Current Balance” on page 14 for more detail on how the average current is measured. Once the average current exceeds 100µA, a comparator triggers the converter to begin overcurrent protection procedures. The Core regulator and ...
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Power Savings Mode feature. The parameters that can be adjusted through the are: 1. Voltage Margining Offset: The DAC voltage can be offset in 25mV increments. 2. VDDPWRGD Trip Level: The PGOOD ...
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ISL6324A I C Slave Address 2 All devices on the I C bus must have a 7-Bit I order to be recognized. The address for the ISL6324A is 1000_110. 2 Communicating Over the I C Bus Two transactions are ...
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R/W bit set to 1, indicating a read. The ISL6324A will then respond by sending the master an Acknowledge, followed by the data byte stored in register RGS1. The master must then ...
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Register Bit Definitions The bits for RGS1 and RGS2 are utilized in the same manner by the ISL6324A (see Table 5). Bit-7 enables the overvoltage protection trip point to be increased. Bit-6 enables the Power-good trip point to be increased. ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following sections. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
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Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times, the lower-MOSFET body-diode reverse recovery charge, Q and the upper MOSFET r conduction loss. DS(ON) When the upper MOSFET turns off, the lower MOSFET does not ...
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Equations 26 and 27, respectively. ⋅ VCC = + + Qg_TOT Qg_Q1 Qg_Q2 Q 3 ⋅ ⋅ ⋅ ⋅ ...
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R resistor for the North Bridge inductor RC filter is left 2 unpopulated and Choose a capacitor value for the North Bridge RC filter. A 0.1µF capacitor is a recommended starting point. 4. Calculate the ...
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Calculate the value for the R resistor using Equation 44: SET ⋅ DCR K ⎛ 400 CORE ⋅ ⋅ ⎜ --------- - -------------------------------------- - = SET ⋅ OCP 3 100μA N ⎝ CORE Where ...
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R in this situation, please refer to “Compensation Without FB Loadline Regulation” on page 33. Compensation With Loadline Regulation The load-line regulated converter behaves in a similar manner to a peak current mode controller because the two poles at the ...
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COMP VSEN FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE REGULATION . ⋅ C ESR ⋅ ------------------------------------------- - ⋅ ⋅ ESR ...
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Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates ...
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Use the same approach for selecting the bulk capacitor type and number. Low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 R APA C APA LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 C C FILTER VCC BOOT2 FS UGATE2 R FS PHASE2 R SET ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 39 ...