ISL6323BCRZ Intersil, ISL6323BCRZ Datasheet
ISL6323BCRZ
Specifications of ISL6323BCRZ
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ISL6323BCRZ Summary of contents
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... PART NUMBER PART RANGE (Note) MARKING (°C) ISL6323BCRZ* ISL6323B CRZ 7x7 QFN L48.7x7 ISL6323BIRZ* ISL6323B IRZ - 7x7 QFN L48.7x7 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special ...
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Pinout FB_NB 1 ISEN_NB+ 2 RGND_NB 3 VID0/VFIXEN 4 VID1/SEL 5 VID2/SVD 6 7 VID3/SVC 8 VID4 9 VID5 10 VCC RGND Integrated Driver Block Diagram PWM SOFT-START AND CONTROL FAULT LOGIC 2 ISL6323B ISL6323B ISL6323B (48 ...
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Controller Block Diagram NB_REF ISEN_NB+ CURRENT SENSE ISEN_NB- VDDPWRGD APA APA COMP OFFSET OFS FB E/A DVC 2X ∑ RGND PWROK VID0/VFIXEN SVI VID1/SEL SLAVE BUS VID2/SVD AND VID3/SVC PVI DAC VID4 VID5 NB_REF OV LOGIC VSEN UV LOGIC RESISTOR ...
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Typical Application - SVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 OFS UGATE2 FS PHASE2 +5V LGATE2 RSET VFIXEN ISEN2- SEL ISEN2+ SVD SVC RGND VID4 NC VID5 ...
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Typical Application - PVI Mode FB VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 VCC BOOT2 OFS UGATE2 FS PHASE2 +5V LGATE2 RSET VID0 ISEN2- VID1/SEL ISEN2+ VID2 VID3 RGND VID4 VID5 NC ...
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... Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below BOOT-PHASE - 0. 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V BOOT Recommended Operating Conditions VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature ISL6323BCRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6323BIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C TEST CONDITIONS high VCC high PVCC1_2 high PVCC_NB ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER VDDPWRGD Sink Current PWM Channel Disable ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Core Undervoltage Threshold NB Undervoltage Threshold ...
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Timing Diagram t PDHUGATE UGATE LGATE t FLGATE Functional Pin Description VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6323B. If the pin is LO prior to enable, ...
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... MOSFETs’ gates. PWM3 and PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable them and configure the core VR controller for 2- or 3-phase operation ...
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ISEN_NB-, ISEN_NB+ These pins are used for differentially sensing the North Bridge output current. The sensed current is used for protection and load line regulation if droop is enabled. Connect ISEN_NB- to the node between the RC sense element surrounding ...
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... PWM signal can occur is generated by an internal clock, whose cycle time is the inverse of the switching frequency set by the resistor between the FS pin and ground. The advantage of Intersil’s proprietary Active Pulse 12 ISL6323B Positioning (APP) modulator is that the PWM signal has the ...
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ISL6323B INTERNAL CIRCUIT EXTERNAL CIRCUIT APA - 100µ APA APA APA,TRIP FILTER COMP AMPLIFIER FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION The APA trip level is the amount of DC offset between the COMP pin and the APA ...
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... VCC the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel RSET pulse width based on the error. Intersil’s patented R SET current-balance method is illustrated in Figure 6, with error correction for Channel 1 represented. In the figure, the cycle ...
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VID1/SEL pin. When the EN pin is toggled HIGH, the status of the VID1/SEL pin will latch the ISL6323B into either PVI or SVI mode. This latching occurs on the rising edge of the EN signal. If ...
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PRE-PWROK METAL VID Typical motherboard start-up occurs with the VFIXEN input low. The controller decodes the SVC and SVD inputs to determine the Pre-PWROK metal VID setting. Once the POR circuitry is satisfied, the ISL6323B begins decoding the inputs per ...
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SVI MODE Once the controller has successfully soft-started and VDDPWRGD transitions high, the Northbridge SVI interface can assert PWROK to signal the ISL6323B to prepare for SVI commands. The controller actively monitors the SVI interface for set VID commands to ...
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... OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6323B to include the combined tolerances of each of these elements. The output of the error amplifier, V COMP modulator to generate the PWM signals ...
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Output-Voltage Offset Programming The ISL6323B allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to ...
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This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current the ISL6323B ...
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... ICs reach their rising POR level before the ISL6323B becomes enabled. The schematic in Figure 12 demonstrates sequencing the ISL6323B with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. When selecting the value of the resistor divider the driver maximum rising POR threshold should be used for calculating the proper resistor values ...
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OUTPUT PRECHARGED ABOVE DAC LEVEL OUTPUT PRECHARGED BELOW DAC LEVEL V CORE 400mV/DIV EN 5V/DIV 100µs/DIV FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323B-BASED MULTI-PHASE CONVERTER Fault Monitoring and Protection The ISL6323B actively monitors both CORE and NB output voltages and currents ...
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Undervoltage Detection The undervoltage threshold is set at VDAC - 300mV typical. When the output voltage (VSEN-RGND) is below the undervoltage threshold, PGOOD gets pulled low. No other action is taken by the controller. PGOOD will return high if the ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. ...
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A third component involves the lower MOSFET reverse-recovery charge Since the inductor current has rr fully commutated to the upper MOSFET before the lower-MOSFET body diode can recover all of Q conducted through the upper MOSFET across VIN. ...
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In Equations 28 and 29 the total upper gate drive Qg_Q1 power loss and P is the total lower gate drive power Qg_Q2 loss; the gate charge (Q and defined at the G1 G2 particular ...
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Calculate the values for R and R 1 Equations 35 and 36 will allow for their computation Core K ---------------------------------------------- = Core Core ⋅ Core Core Core ...
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Inductor DCR Current Sensing Component Fine Tuning V IN UGATE(n) MOSFET DRIVER LGATE(n) INDUCTOR R ISL6323B INTERNAL CIRCUIT I n 40kΩ ---------------- - SET SAMPLE + V ( ISEN 2.4kΩ ...
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C (OPTIONAL COMP VSEN FIGURE 22. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6323B CIRCUIT Since the system poles and zero are affected by the values of the components that are meant to compensate ...
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C ESR ⋅ ------------------------------------------- - 1 FB ⋅ ⋅ – C ESR ⋅ ⋅ – C ESR C = ------------------------------------------- - ⋅ 0. ---------------------------------------------------------------------------------------------------- ...
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The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV . This places an upper limit on inductance. MAX Equation 56 gives the ...
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Low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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VSEN COMP BOOT1 ISEN3+ ISEN3- UGATE1 PWM3 PHASE1 R APA C APA LGATE1 APA ISEN1- DVC ISEN1+ +5V PVCC1_2 C C FILTER VCC OFS BOOT2 R OFS UGATE2 FS PHASE2 +5V ...
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Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 7.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 35 ...