ISL62881HRTZ-T Intersil, ISL62881HRTZ-T Datasheet - Page 22

• Manufacturer Part Number: ISL62881HRTZ-T
• Description: IC REG PWM SGL PHASE 28TQFN
• Manufacturer: Intersil

Specifications of ISL62881HRTZ-T

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate of 2.5µs or 1.25µs per tick
(12.5mV), controlling output voltage V
5mV/µs or 10mV/µs.
Figure 23 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
V
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I
voltage V
Similar behavior occurs during the down transition.
To control V
one can add the R
cancels I
FIGURE 23. OPTIONAL SLEW RATE COMPENSATION
droop_vid
core
Idroop_vid
COMP
slew rate. Ideally, V
VID<0:6>
droop_vid
core
Vcore
waveform shows, and will droop the output
INTERNAL TO
core
Ivid
Vfb
CIRCUIT FOR1-TICK VID TRANSITION
accordingly, making V
E/A
IC
slew rate during 1-tick VID transition,
.
vid
FB
-C
Σ
vid
Idroop_vid
VDAC
core
22
branch, whose current I
R
Rdroop
vid
DAC
will follow the FB pin
I
X 1
vid
C
vid
core
RTN
VIDs
VSS
core
slew rate slow.
OPTIONAL
ISL62881, ISL62881B
Vcore
VID<0:6>
slew rate at
VSS
SENSE
vid
When V
induced I
where C
In the meantime, the R
domain expression is as shown in Equation 32:
It is desired to let I
are:
and:
The result is:
and:
For example: given LL = 3mΩ, R
C
dV
and Equation 36 gives C
It’s recommended to select the calculated R
start with the calculated C
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The R
ground and the real ground, and hence has no effect on
transient response.
Voltage Regulator Thermal Throttling
Figure 24 shows the thermal throttling feature with
hysteresis. An NTC network is connected between the
NTC pin and GND. At low temperature, SW1 is on and
SW2 connects to the 1.20V side. The total current
flowing out of the NTC pin is 60µA. The voltage on NTC
pin is higher than the threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the
external resistor.
C
I
C
R
R
I
droop
vid
out
vid
vid
vid
vid
fb
t ( )
×
×
/dt = 15mV/µs, Equation 35 gives R
=
=
= 1320µF, dV
t ( )
dV
------------
C
=
C
------------------------- -
R
dt
vid
core
R
out
out
droop
C
fb
=
droop
droop
vid
C
------------------------- -
=
=
×
R
is the total output capacitance.
increases, the time domain expression of the
out
×
C
LL
vid
C
------------------------- -
droop
R
dV
------------
out
out
change is as shown in Equation 31:
×
dt
droop
×
-C
LL
fb
------------------ -
×
dV
------------------ -
×
vid
dV
------------
LL
×
LL
dt
dt
vid
×
core
core
⎛
⎜
⎜
⎝
fb
dV
------------------ -
1 e
network is between the virtual
×
(t) cancel I
–
dt
dV
------------------ -
core
vid
/dt = 5mV/µs and
------------------------------- -
R vid C vid
dt
core
vid
-C
vid
×
vid
t –
⎛
⎜
⎜
⎝
×
= 227pF.
1 e
value and tweak it on the
–
branch current I
droop_vid
-------------------------- -
C
⎞
⎟
⎟
⎠
droop
out
t –
×
LL
= 4.22kΩ,
⎞
⎟
⎟
⎠
(t). So there
vid
vid
= 4.22kΩ
March 9, 2011
value and
vid
(EQ. 31)
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
(EQ. 36)
FN6924.2
time