ISL6267HRZ-T Intersil, ISL6267HRZ-T Datasheet - Page 14

• Manufacturer Part Number: ISL6267HRZ-T
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ-T

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
Multiphase R
The ISL6267 is a multiphase regulator implementing two voltage
regulators, VDD and VDDNB, on one chip controlled by AMD’s™
SVI1™ protocol. VDD can be programmed for 1-, 2- or 3-phase
operation. VDDNB can be configured for 1- or 2-phase operation.
Both regulators use the Intersil patented R
Regulator) modulator. The R
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 7 conceptually
shows the multiphase R
the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called “VW window” in the following
discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C
to g
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If V
mode, the master clock signal is distributed to the three phases,
and the Clock 1~3 signals will be 120° out-of-phase. If VR1 is in
2-phase mode, the master clock signal is distributed to Phases 1
and 2, and the Clock1 and Clock2 signals will be 180° out-of-
CRS1
CRS2
CRS3
m
GMVO
V
o
, where g
MASTER
CLOCK
VCRS1
VCRS2
VCRS3
FIGURE 7. R
VW
VW
VW
VW
VCRM
m
CRM
COMP
3
is a gain factor. C
™ Modulator
CLOCK3
CLOCK2
CLOCK1
3
MASTER CLOCK CIRCUIT
™ modulator circuit, and Figure 8 shows
GM
GM
GM
3
™
3
SLAVE CIRCUIT 1
SLAVE CIRCUIT 2
SLAVE CIRCUIT 3
™ modulator combines the best
MASTER
MODULATOR CIRCUIT
CLOCK
14
S
R
S
R
S
R
Q
Q
Q
rm
PWM1
PWM2
PWM3
SEQUENCER
with a current source equal
rm
PHASE
voltage V
PHASE1
PHASE2
PHASE3
3
™ (Robust Ripple
DD
CLOCK1
CLOCK2
CLOCK3
is in 3-phase
L1
L2
L3
I
I
I
CRM
L1
L2
L3
is a
VO
CO
ISL6267
phase. If VR1 is in 1-phase mode, the master clock signal will be
distributed to Phase 1 only and be the Clock1 signal.
Each slave circuit has its own ripple capacitor C
mimics the inductor ripple current. A g
inductor voltage into a current source to charge and discharge
C
clock signal, and the current source charges C
voltage V
and the current source discharges C
Since the controller works with V
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6267 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6267 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
rs
MASTER
CLOCK3
. The slave circuit turns on its PWM pulse upon receiving the
CLOCK1
CLOCK2
CLOCK
FIGURE 8. R
VCRM
COMP
PWM1
PWM2
PWM3
VW
Crs
hits VW, the slave circuit turns off the PWM pulse,
STEADY STATE
VCRS2
3
™
MODULATOR OPERATION PRINCIPLES IN
VW
VCRS3
crs
VCRS1
, which are large amplitude
rs
.
m
amplifier converts the
HYSTERETIC
WINDOW
rs
rs
. When C
, whose voltage
January 31, 2011
rs
FN7801.0