ISL6267HRZ Intersil, ISL6267HRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6267HRZ
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions (see Figure 14). During a send
byte transaction, the processor sends the start sequence
followed by the slave address of the VR for which the VID
command applies. The address byte must be configured
according to Table 3. The processor then sends the write bit. After
the write bit, if the ISL6267 receives a valid address byte, it
sends the acknowledge bit. The processor then sends the PSI-L
bit and VID bits during the data phase. The Serial VID 8-bit data
field encoding is outlined in Table 4. If ISL6267 receives a valid
8-bit code during the data phase, it sends the acknowledge bit.
Finally, the processor sends the stop sequence. After the
ISL6267 has detected the stop, it can then proceed with the
VID-on-the-fly transition.
Operation
After the start-up sequence, the ISL6267 begins regulating the
Core and Northbridge output voltages to the pre-PWROK metal
VID programmed. The controller monitors SVI commands to
determine when to enter power-saving mode, implement
dynamic VID changes, and shut down individual outputs.
BITS
BITS
6:4
6:0
3
2
1
0
7
SVD
PSI_L:
=0 means the processor is at an optimal load for the regulators
to enter power-saving mode
=1 means the processor is not at an optimal load for the
regulators to enter power-saving mode
SVID[6:0] as defined in Table 2.
SVC
Always 110b
Reserved by AMD for future use
VDD1; if set, then the following data byte contains the VID for
VDD1 [Note: The ISL6267 does not support VDD1]
VDD0; if set, then the following data byte contains the VID for
VID0
VDDNB; if set then the following data byte contains the VID for
VIDNB
TABLE 4. SERIAL VID 8-BIT DATA FIELD ENCODING
TABLE 3. SVI SEND BYTE ADDRESS DESCRIPTION
6
DESCRIPTION
DESCRIPTION
19
SLAVE ADDRESS PHASE
5
4
3
2
FIGURE 14. SEND BYTE EXAMPLE
1
0
ISL6267
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the PROG1 pin and the Northbridge in a
similar manner from the PROG2 pin. Table 5 provides the resistor
value to select the desired output voltage offset
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL6267 regulates the output voltage
to the value set by the VID information, per Table 2. The ISL6267
controls the no-load output voltage to an accuracy of ±0.5% over
the range of 0.75V to 1.55V. A differential amplifier allows
voltage sensing for precise voltage regulation at the
microprocessor die.
7
RESISTOR VALUE
6
11500
14000
16500
18700
1100
1690
2260
4320
5620
6650
7870
9530
OPEN
3160
590
[Ω]
5
0
DATA PHASE
TABLE 5. PROGx PIN RESISTOR VALUE
See Table 3
4
SVID
3
2
V
CORE OFFSET
1
PROG1
-12.50
-18.75
-25.00
-31.25
-43.75
-37.50
43.75
31.25
25.00
18.75
12.50
37.50
-6.25
6.25
0.00
50
0
[mV]
OFFSET [mV]
January 31, 2011
PROG1
-12.50
-18.75
-25.00
-31.25
-43.75
-37.50
43.75
31.25
25.00
18.75
12.50
37.50
-6.25
6.25
0.00
VNB
50
FN7801.0