ISL8033AIRZ-T Intersil, ISL8033AIRZ-T Datasheet - Page 4

• Manufacturer Part Number: ISL8033AIRZ-T
• Description: IC REG SYNC BUCK DUAL 3A 24QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of ISL8033AIRZ-T

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 V ~ 6 V
• Current - Output: 3A
• Frequency - Switching: 2.5MHz
• Voltage - Input: 2.85 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configuration
Pin Descriptions
PIN NUMBER
22, 23
20, 21
1, 24
7, 8
10
11
12
13
14
15
4
9
5
6
SYMBOL
PGND2
PGND1
SGND
SYNC
PG2
PG1
ISET
VDD
LX2
EN2
FB2
FB1
EN1
NC
4
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and
discharge output capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT2 voltage.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier.
The output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output
voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. There
is an internal compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the Channel 2
regulator output voltage.
No connect pins. Please tie to GROUND.
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error
amplifier. The output voltage is set by an external resistor divider connected to FB1. With a properly selected
divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the
0.8V reference. There is an internal compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the Channel 1
regulator output voltage.
System ground. Make a single point connection from these pins to PGND.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT1 voltage.
Connect to logic high or input voltage VIN. Connect to an external function generator for external Synchronization.
Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and
discharge output capacitor when driven to low. Do not leave this pin floating.
ISET is the output current limit setting of the regulators. See the “” table on page 6 for settings.
Input supply voltage for the logic. Connect VIN pin.
Negative supply for the power stage of Channel 1.
VIN2
VIN2
EN2
PG2
FB2
LX2
ISL8033, ISL8033A
1
2
3
4
5
6
24
7
ISL8033, ISL8033A
23
8
(24 LD QFN)
TOP VIEW
22
9
PD
25
21
10
11
20
12
19
DESCRIPTION
18
17
16
15
14
13
LX1
VIN1
VIN1
VDD
ISET
EN1
March 24, 2011
FN6854.2