TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 46

MOD ADC DAC TOWER LINEAR TECH

TWR-ADCDAC-LTC

Manufacturer Part Number
TWR-ADCDAC-LTC
Description
MOD ADC DAC TOWER LINEAR TECH
Manufacturer
Freescale Semiconductor
Type
A/Dr
Datasheets

Specifications of TWR-ADCDAC-LTC

Main Purpose
Data Conversion, ADC, DAC
Embedded
No
Utilized Ic / Part
LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
Primary Attributes
2 Analog to Digital Converters, 2 Digital to Analog Converters
Secondary Attributes
For use with Freescale Tower System
Maximum Clock Frequency
50 MHz
Interface Type
Touch Sense, ULPI, UART, IrDA, I2S,
Product
Data Conversion Development Tools
Silicon Manufacturer
Freescale
Silicon Core Number
LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
Kit Application Type
Data Converter
Application Sub Type
ADC, DAC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Kinetis MCU
Lead Free Status / Rohs Status
Compliant
between two clock sources:
bits.
clock cycles of being unlocked.
cycles.
can be permanently disabled.
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Independent clock source input (independent from CPU/Bus clock). Choice
Unlock sequence for allowing updates to write-once WDOG Control/Configuration
All WDOG Control/Configuration bits are writeable once only, within 256 bus
Programmable Timeout period, specified in terms of number of WDOG clock
Ability to test WDOG timer and reset, with flag indicating watchdog test. This test
1 KHz Internal Oscillator (external to the WDOG)
Bus clock
Users need to always update these after unlocking, within 256 bus clock cycles.
Failure to update resets the system.
Quick Test – Small timeout value programmed for quick test.
Byte Test – Individual bytes of timer tested one at a time.
47
WDOG Features
TM

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