TWR-ADCDAC-LTC Freescale Semiconductor, TWR-ADCDAC-LTC Datasheet - Page 47

• Manufacturer Part Number: TWR-ADCDAC-LTC
• Description: MOD ADC DAC TOWER LINEAR TECH
• Manufacturer: Freescale Semiconductor
• Type: A/Dr

Specifications of TWR-ADCDAC-LTC

• Main Purpose: Data Conversion, ADC, DAC
• Embedded: No
• Utilized Ic / Part: LTC1859, LTC2498, LTC2600, LTC2704, LTC3471
• Primary Attributes: 2 Analog to Digital Converters, 2 Digital to Analog Converters
• Secondary Attributes: For use with Freescale Tower System
• Maximum Clock Frequency: 50 MHz
• Interface Type: Touch Sense, ULPI, UART, IrDA, I2S,
• Product: Data Conversion Development Tools
• Silicon Manufacturer: Freescale
• Silicon Core Number: LTC2704, LTC2600, LTC1859, LTC2498, LTC3471 & LTC6655-5
• Kit Application Type: Data Converter
• Application Sub Type: ADC, DAC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Kinetis MCU
• Lead Free Status / Rohs Status: Compliant

►
►
►
►
►
test mechanisms to ensure safe operation of hardware and software in application
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
Read only Access to WDOG timer
Windowed Refresh Option
Robust refresh mechanism
Count of WDOG resets as they occur.
Class B: IEC 60730 compliant by providing system robustness, diagnostic and self
•
•
•
•
•
•
Allows dynamic check that WDOG timer is operational
Provides robust check that program flow is faster than expected.
Programmable window.
Refresh outside window leads to reset.
Write values of 0xA602 and then 0xB480, within 20 bus clock cycles of each
other, to WDOG Refresh Register.
Configurable interrupt on timeout to provide "debug breadcrumbs". This is
followed by a reset after 256 bus clock cycles.
48
WDOG Features
TM