ISLA110P50IR72EV1Z Intersil, ISLA110P50IR72EV1Z Datasheet - Page 25

• Manufacturer Part Number: ISLA110P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA110P50IR72
• Manufacturer: Intersil

Specifications of ISLA110P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to
configure I2E’s dynamic freeze control. As with any
interleave mismatch correction algorithm making
estimates of the interleave mismatch errors using the
digitized application input signal, there are certain
characteristics of the input signal that can obscure the
mismatch estimates. For example, a DC input to the A/D
contains no information about the sample time skew
mismatch between the core A/Ds, and thus should not be
used by the I2E algorithm to update its sample time
skew estimate. Under such circumstances, I2E enters
Hold state. In the Hold state, the analog adjustments will
be frozen and mismatch estimate calculations will cease
until such time as the analog input achieves sufficient
quality to allow the I2E algorithm to make mismatch
estimates again.
These registers allow the programming of the thresholds
of the meters used to determine the quality of the input
signal. This can be used by the application to optimize
I2E’s behavior based on knowledge of the input signal.
For example, if a specific application had an input signal
that was typically 30dB down from full scale, and was
primarily concerned about analog performance of the
A/D at this input power, lowering the RMS power
threshold would allow I2E to continue tracking with this
input power level, thus allowing it to track over voltage
and temperature changes.
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
This 16-bit quantity is the RMS power threshold at which
I2E will enter Hold state. The RMS power of the analog
input is calculated continuously by I2E on incoming data.
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are MSB-
aligned to 12-bit data). A dynamic number of these 24-
bit results are averaged to compare with this threshold
approximately every 1
freeze I2E. The 24-bit threshold is constructed with bits
23 through 20 (MSBs) assigned to 0, bits 19 through 4
assigned to this 16-bit quantity, and bits 3 through 0
(LSBs) assigned to 0. As an example, if the application
wanted to set this threshold to trigger near the RMS
analog input of a -20dBFS sinusoidal input, the
calculation to determine this register’s value would be
RMS
hex 290
Therefore, programming 0x1488 into these two registers
will cause I2E to freeze when the signal being digitized
has less RMS power than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E
to freeze when the input amplitude is less than -21.2
dBFS.
(
codes
2
)
=
=
0x014884
------ -
2
2
×
10
⎛
⎝
–
---------
20
20
TruncateMSBandLSBhexdigit
⎞
⎠
µ
×
s to decide whether or not to
2
12
25
≅
290codes
=
0x1488
ISLA110P50
(EQ. 2)
(EQ. 3)
The freezing of I2E by the RMS power meter threshold
affects the gain and sample time skew interleave
mismatch estimates, but not the offset mismatch
estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating
between the Hold and Track state, there is hysteresis in
the comparison described above. After I2E enters a
frozen state, the RMS input power must achieve ≥
threshold value + hysteresis to again enter the Track
state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being
assigned to 0, bits 11 through 4 assigned to this
register’s value, and bits 3 through 0 (LSBs) assigned to
0.
AC RMS Power Threshold
Similar to RMS power threshold, there must be sufficient
AC RMS power (or dV/dt) of the input signal to measure
sample time skew mismatch for an arbitrary input. This is
clear from observing the effect when a high voltage (and
therefore large RMS value) DC input is applied to the A/D
input. Without sufficient dV/dt in the input signal, no
information about the sample time skew between the
core A/Ds can be determined from the digitized samples.
The AC RMS Power Meter is implemented as a high-
passed (via DSP) RMS power meter.
The writing of the AC RMS Power Threshold is different
than other SPI registers, and these registers are not
listed in the SPI memory map table. The required
algorithm is documented below.
A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are
MSB-aligned to 12-bit data). A dynamic number of these
24-bit results are averaged to compare with this
threshold approximately every 1
not to freeze I2E. The 24-bit threshold is constructed
with bits 23 through 20 (MSBs) assigned to 0, bits 19
through 4 assigned to this 16-bit quantity, and bits 3
through 0 (LSBs) assigned to 0. The calculation
methodology to set this register is identical to the
description in the RMS power threshold description.
The freezing of I2E when the AC RMS power meter
threshold is not met affects the sample time skew
interleave mismatch estimate, but not the offset or gain
mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between
the Hold and Track state, there is hysteresis in the
comparison described above. After I2E enters a frozen
state, the AC RMS input power must achieve ≥ threshold
1. Write the value 0x80 to the Index Register (SPI
2. Write the MSBs of the 16-bit quantity to SPI Address
3. Write the LSBs of the 16-bit quantity to SPI Address
address 0x10)
0x150
0x14F
µ
s to decide whether or
June 4, 2010
FN7606.1