ADC16DV160HFEB/NOPB National Semiconductor, ADC16DV160HFEB/NOPB Datasheet - Page 20

• Manufacturer Part Number: ADC16DV160HFEB/NOPB
• Description: EVAL BOARD FOR ADC16DV160
• Manufacturer: National Semiconductor

Specifications of ADC16DV160HFEB/NOPB

• Number Of Adc's: *
• Number Of Bits: 16
• Sampling Rate (per Second): 160M
• Data Interface: *
• Inputs Per Adc: *
• Input Range: *
• Voltage Supply Source: Analog and Digital
• Utilized Ic / Part: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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the ADC16DV160. Power supplies for the clock drivers have
to be separated from the ADC output driver supplies to pre-
vent modulating the clock signal with the ADC digital output
signals. Higher noise floor and/or increased distortion/spur
may result from any coupling of noise from the ADC digital
output signals to the analog input and clock signals.
In IF sampling applications, the signal-to-noise ratio is partic-
ularly affected by clock jitter as shown in
4.0 CALIBRATION
The automatic calibration engine contained within the AD-
C16DV160 improves dynamic performance and reduces its
part-to-part variation. Digital output signals including output
clock (OUTCLK+/-) are all logic low while calibrating. The AD-
C16DV160 is automatically calibrated when the device is
powered up. Optimal dynamic performance might not be ob-
tained if the power-up time is longer than the internal delay
time (~32 mS @ 160 MSPS clock rate). In this case, the AD-
C16DV160 can be re-calibrated by asserting and then de-
asserting power down mode. Re-calibration is recommended
whenever the operating clock rate changes.
5.0 VOLTAGE REFERENCE
A stable and low-noise voltage reference and its buffer am-
plifier are built into the ADC16DV160. The input full scale is
FIGURE 12. SNR with given Jitter vs. Input Frequency
Figure
12. Tj is the
20
integrated noise power of the clock signal divided by the slope
of clock signal around the tripping point. The upper limit of the
noise integration is independent of applications and set by the
bandwidth of the clock signal path. However, the lower limit
of the noise integration highly relies on the application. In base
station receive channel applications, the lower limit is deter-
mined by the channel bandwidth and space from an adjacent
channel.
two times V
bandgap output with a 10 kΩ output impedance) as well as
V
adjusted by changing V
external reference with low output impedance can easily over-
drive the V
mon mode voltage (V
Maximum SNR can be achieved at the maximum input range
where V
and static performance is optimized at a V
ing V
of the ADC16DV160's SNR performance.
RP
- V
REF
RN
REF
can improve SFDR performance by sacrificing some
REF
as shown in
REF
= 1.2V. Although the ADC16DV160's dynamic
pin. The default V
, which is the same as VBG (the on-chip
30101435
RM
REF
Figure
) is a fixed voltage level of 1.15V.
either internally or externally. An
13. The input range can be
REF
is 1.2V. The input com-
REF
of 1.2V, reduc-